Journal Article10.1016/J.MEJO.2008.11.044
IDEA and AES, two cryptographic algorithms implemented using partial and dynamic reconfiguration
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TL;DR: This work presents the experience in implementing two different cryptographic algorithms in an FPGA: IDEA and AES, done by means of mixing Handel-C and VHDL and using partial and dynamic reconfiguration to reach very high performance.
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About: This article is published in Microelectronics Journal. The article was published on 01 Jun 2009. The article focuses on the topics: Control reconfiguration & VHDL.
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Citations
[서평]「Applied Cryptography」
염흥렬
- 01 Apr 1997
TL;DR: The objective of this paper is to give a comprehensive introduction to applied cryptography with an engineer or computer scientist in mind on the knowledge needed to create practical systems which supports integrity, confidentiality, or authenticity.
2.1K
FPGA schemes for minimizing the power-throughput trade-off in executing the Advanced Encryption Standard algorithm
TL;DR: The results show that the proposed schemes are able to reduce the logic and signal power by 60% and 27%, respectively on a Virtex 2 Pro FPGA while maintaining a high level of throughput.
44
Real-time embedded systems powered by FPGA dynamic partial self-reconfiguration: a case study oriented to biometric recognition applications
TL;DR: The results let point out biometric recognition as a sensible killer application for run-time reconfigurable computing, mainly in terms of efficiently balancing computational power, functional flexibility and cost.
25
Design and implementation of an ASIP-based cryptography processor for AES, IDEA, and MD5
TL;DR: A new 32-bit ASIP-based crypto processor for AES, IDEA, and MD5 is designed and the performance is compared to some previous and state-of-the-art implementations in terms of speed, latency, throughput, and flexibility.
25
•Journal Article
Single-chip FPGA implementation of the advanced encryption standard algorithm
M. McLoone,John V. McCanny +1 more
TL;DR: The FPGA implementation described here is that of a fully pipelined single-chip Rijndael design which runs at a data rate of 7 Gbits/sec on a Xilinx Virtex-E XCV812E-8-BG560 FPGAs device, which proves to be one of the fastest single- chip RIJndael implementations currently available.
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References
[서평]「Applied Cryptography」
염흥렬
- 01 Apr 1997
TL;DR: The objective of this paper is to give a comprehensive introduction to applied cryptography with an engineer or computer scientist in mind on the knowledge needed to create practical systems which supports integrity, confidentiality, or authenticity.
2.1K
High-speed VLSI architectures for the AES algorithm
Xinmiao Zhang,Keshab K. Parhi +1 more
TL;DR: Using the proposed architecture, a fully subpipelined encryptor with 7 substages in each round unit can achieve a throughput of 21.56 Gbps on a Xilinx XCV1000 e-8 bg560 device in non-feedback modes, which is faster and 79% more efficient in terms of equivalent throughput/slice than the fastest previous FPGA implementation known to date.
The Block Cipher Rijndael
Joan Daemen,Vincent Rijmen +1 more
- 14 Sep 1998
TL;DR: The block cipher Rijndael as mentioned in this paper is one of the fifteen candidate algorithms for the Advanced Encryption Standard (AES) and can be implemented very efficiently on smart cards.
401
An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists
TL;DR: This contribution investigates the significance of FPGA implementations of the Advanced Encryption Standard candidate algorithms, with a strong focus on high-throughput implementations, which are required to support security for current and future high bandwidth applications.
322
•Book
Circuit Design with VHDL
Volnei A. Pedroni
- 01 Jan 2004
TL;DR: This book's highly original approach of teaching through extensive system examples as well as its unique integration of VHDL and design make it suitable both for use by students in computer science and electrical engineering.
290