Patent
High transfer rate between multi-processor units
Erik R. Myrmo,Michael F. Wells +1 more
- 28 Jun 1982
33
TL;DR: In this article, direct memory access (DMA) is used for transferring information between data processing units in a multi-processor environment at high throughput rates, where the high throughput rate is achieved by concurrent send/receive direct-memory access transfers between buffer memories associated with each unit.
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Abstract: In the operation of a network of data processing units, a method and apparatus for transferring information between units in a multi-processor environment at high throughput rates. The high throughput rates are achieved by concurrent send/receive direct-memory-access transfers between buffer memories associated with each unit. The invention provides for direct-memory-access (DMA) transfers between a buffer memory and the data port of the sending unit and direct-memory-access transfers between this data port and the buffer memory of the receiving unit; thus eliminating shared-memory resource allocation, memory access arbitration and other programmed operations which normally require execution of several instructions by each unit's processor for each transfer. Each unit interfaces with the system bus through a message transfer facility which groups the buffer memory, the output data port, an attention identification register, resident traffic control DMA and data processors and optional miscellaneous function expansion. Each message transfer is initiated by the sending unit placing on the system bus the address of the targeted receiving unit attention identification register, and the sending unit unique identification. The receiving unit, upon recognizing the identification code in its attention register, initiates the direct-memory-access transfer.
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Citations
Patent
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TL;DR: In this paper, the authors proposed a method for congestion control and avoidance in computer networks, which includes the steps of sensing network congestion (including both sensing and predicting possible future network congestion) and allowing a network node to transmit at least one basic data segment and thereafter to transmit additional data.
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Donald D. Crouse,Kenneth M. Partyka +1 more
- 01 Feb 1993
TL;DR: In this paper, a pipelined, multiprocessor data server includes a common inter-processor bus that connects one or more communication processors and file processors to one or multiple device processors, each having a buffer memory.
65
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Personal computer having dedicated processors for peripheral devices interconnected to the CPU by way of a system control processor
Brian C. Barnes,Mark J. Foster,Lloyd W. Gauthier,Saifee Fakhruddin,David J. DeLisle,David R. Veit +5 more
- 17 Feb 1993
TL;DR: In this paper, a plurality of processors form a network used to communicate with one or more peripheral devices and the system control processor, where each processor is dedicated to at least one peripheral device.
64
Patent
Device interface controller for intercepting communication between a microcomputer and peripheral devices to control data transfers
Gerety Eugene Peter,Jitender K. Vij +1 more
- 25 Feb 1985
TL;DR: In this paper, an apparatus for use with a DMA controller includes a device interface controller having therein both general and specific command programs, and device bus interface, arranged to intercept all communication signals between the controller and a microcomputer associated therewith.
62
Patent
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Barry John Gleeson
- 22 Jan 1993
TL;DR: In this article, a fault tolerant computer system employing primary tasks (31, 41, 51) and corresponding backup tasks (32, 42, 52) operates to provide fault tolerant operation even where uncontrolled external events (Table C and D) may occur whose time of occurrence may affect task performance.
42
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12