Patent
High speed parallel bus and data transfer method
Raymond S. Tetrick,John Beaston,Robert L. Farrell,Alireza Sarabi,Sudarshan Balachandran,Edwin L. Jacks,Steven D. Kassel +6 more
- 25 Nov 1983
141
TL;DR: In this article, a multiple bus system architecture and improved data transfer methods are disclosed for transferring data between a plurality of data processing resources, which includes both a parallel and serial bus which interconnects data processing units and peripheral devices (collectively referred to as "agents") to permit the exchange of data and messages at high speed using a minimum of handshake events before the actual data transfer.
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Abstract: A multiple bus system architecture and improved data transfer methods are disclosed for transferring data between a plurality of data processing resources. The bus structure of the present invention includes both a parallel and serial bus which interconnects data processing units and peripheral devices (collectively referred to as "agents") to permit the exchange of data and messages at high speed using a minimum of "handshake" events prior to the actual data transfer. Both the serial and parallel bus protocals are controlled by message control means coupled to each communicating agent. A local bus is coupled to processing agents within the system such that local memory and secondary processing resources may be accessed without impacting data traffic along the parallel bus. Direct access to resources coupled to the local bus of an agent from other bus agents is also controlled by the message control means.
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Citations
Patent
Integrated circuit I/O using a high performance bus interface
Michael Farmwald,Mark Horowitz +1 more
- 16 Apr 1991
TL;DR: In this article, the authors present a memory subsystem comprising at least two semiconductor devices (15, 16, 17), including at least one memory device connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address.
552
Patent
Code division multiple access (CDMA) communication system
Fatih Ozukturk,Alexander Jacques,Gary R. Lomp,John Kowalski +3 more
- 27 Jun 1996
TL;DR: In this article, a closed loop power control system for maintaining a minimum system transmit power level for a radio carrier station and the subscriber units, and system capacity management for maintaining the maximum number of active subscriber units for improved system performance.
392
Patent
Method for training a communication link between ports to correct for errors
William Patterson Bunton
- 14 Sep 2000
TL;DR: In this paper, a technique for training links in a computing system is disclosed, which includes configuring a first receiver in a first port using a first training sequence or a second training sequence; transmitting the second training sequences from the first port indicating the first receiver is configured; and receiving a second train sequence transmitted by a second port indicating that a second receiver in the second port is configured.
317
Patent
Programmable interface for computer system peripheral circuit card
Stanley John Kopec,Yiu-Fai Chan,Robert F. Hartmann +2 more
- 06 Jul 1989
TL;DR: In this article, a programmable interface for a peripheral circuit card is provided, which can be customized by a user for a particular card design, instead of designing a custom interface chip, the designer can program one or more programmable logic devices on the interface chip to interface with whatever devices are on the peripheral circuit cards.
186
Patent
System for using rapid acquisition spreading codes for spread-spectrum communications
Fatih M. Ozluturk,Gary R. Lomp +1 more
- 21 Dec 2000
TL;DR: In this article, the first long code and the second long code are transmitted at an in-phase (I) and at a quadrature-phase(Q) angle, respectively, on the carrier signal using radio waves.
174
References
Patent
Multi-processor data processing system
Yoshiaki Tokita,Keisuke Okajima +1 more
- 20 Jun 1978
TL;DR: In this paper, a queue buffer accompanied by an intercommunicating information read/write control unit is used to control the transmission and reception of information between the processors and the queue buffer.
85
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