Journal Article10.1109/T-C.1970.223020
High-Speed Computer Multiplication Using a Multiple-Bit Decoding Algorithm
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TL;DR: The binary multiplication algorithm will be discussed first, followed by block decoding method, logic implementation, hardware consideration, and two examples which are at the end of the discussion.
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Abstract: This paper presents a method of performing the binary multiplication beyond the scheme of multiple ADD and SHIFT. The binary multiplication algorithm will be discussed first, followed by block decoding method, logic implementation, hardware consideration, and two examples which are at the end of the discussion.
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Citations
A Binary Multiplication Scheme Based on Squaring
TL;DR: Using the formula A · B=[(A+ B)/2]–(A-B)/2], the binary multiplication problem is reducible to that of decomposing the square of P 0 · P 1 · P 2 · P k into a sum of two or three quantities.
59
Execution Architecture: The DELtran Experiment
TL;DR: This paper reviews the general notion of DEL's, and shows how they compare to traditional instruction set architectures, and focuses on general techniques for synthesizing DEL's rather than performance questions per se.
32
On Binary Multiplication Using the Quarter Square Algorithm
Jayashree,Basu +1 more
TL;DR: This correspondence suggests a new method of perporming binary multiplication using the quarter square technique that is faster, more systematic, and economical than the earlier schemes.
25
A Low Power High Performance Radix-4 Approximate Squaring Circuit
Satyendra Datla,Mitchell A. Thornton,David W. Matula +2 more
- 07 Jul 2009
TL;DR: The results show the radix-4 squaring circuit is power, area and performance efficient, yielding reduction factors by three or more when compared to a truncated multiplication approach using state-of-the-art logic synthesis tools.
25
Higher Radix Squaring Operations Employing Left-to-Right Dual Recoding
David W. Matula
- 08 Jun 2009
TL;DR: A novel left-to-right leading digit first dual recoding of an operand for the purpose of designing the squaring operation on that operand yields an array of non-negative partial squares of size essentially one half that of a comparable multiplier partial product array for both radix-4 and radIX-8 designs.
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References
The IBM system/360 model 91: floating-point execution unit
TL;DR: The principal requirement for the Model 91 floating-point execution unit was that it be designed to support the instructionissuing rate of the processor, so separate, instruction-oriented algorithms for the add, multiply, and divide functions were developed.