Patent
Graphics system with graphics controller and DRAM controller
Jean-Michel Callemyn
- 21 Dec 1988
86
TL;DR: In this paper, a graphics system comprising a screen processor, a bus arbitrator to arbitrate the requests for access to a single word and to select a request, and a DRAM DRAM Dynamic Random Access Memory, controller, arbitrate requests for a plurality of words and the refresh requests.
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Abstract: A graphics system comprising a screen processor which separately formulates the requests for access to a single word and the requests for access to a plurality of consecutive words, a bus arbitrator to arbitrate the requests for access to a single word and to select a request, and a DRAM Dynamic Random Access Memory, controller to arbitrate the requests for a plurality of words and the refresh requests. The DRAM controller preferably comprises an automatic system which directly generates line and column control signals. The automatic system is preferably constructed in the form of a PLA (Program Logic Array).
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Citations
Patent
Multistandard video decoder and decompression system for processing encoded bit streams including a video formatter and methods relating thereto
Adrian Philip Wise,Martin William Sotheran,William Philip Robbins,Anthony Mark Jones,Helen Rosemary Finch,Kevin James Boyd,Anthony Peter John Claydon +6 more
- 26 Jan 2001
TL;DR: In this article, a pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bits stream.
249
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Data pipeline system and data encoding method
Adrian Philip Wise,Martin William Sotheran,William Philip Robbins +2 more
- 07 Jun 1995
TL;DR: In this article, a pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bits stream.
189
Patent
Method and apparatus for gigabit packet assignment for multithreaded packet processing
Gilbert Wolrich,Debra Bernstein,Matthew J. Adiletta,Donald Hooper +3 more
- 07 Dec 2000
TL;DR: In this article, a network processor that has multiple processing elements, each supporting multiple simultaneous program threads with access to shared resources in an interface, is presented, where packet data is received from high-speed ports in segments and each segment is assigned to one of the program threads.
143
Patent
Token-based adaptive video processing arrangement
Adrian Philip Wise,Kevin D. Dewar,Anthony Mark Jones,Martin William Sotheran,Colin Smith,Helen Rosemary Finch,Anthony Peter John Claydon,Donald William Walke Patterson,Mark Barnes,Andrew Peter Kuligowski,William Philip Robbins,Nicholas Birch,David Andrew Barnes +12 more
- 07 Jun 1995
TL;DR: In this article, an MPEG-video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine is described. But the authors do not specify the corresponding decoding circuits.
129
References
Patent
Bus arbitrating circuit
Ralph L. Adcock
- 08 Sep 1981
TL;DR: In this article, the authors described a circuit which controls or arbitrates access to a memory unit among a plurality of data processing units and manages pointers to different sections of the memory upon a simple one byte request.
39
Patent
Display memory control system
Yutaka Yoshiba
- 20 Apr 1987
TL;DR: In this paper, a display memory control system is described which is associated with a display system for displaying and outputting character data, graphic data and the like, in the event of displaying images on a display, a system (host computer) writes one screen of display data in one of two VRAMs.
33
Patent
Computer memory refresh circuit
Toyota Honda,Shigeru Hirahata +1 more
- 26 Nov 1984
TL;DR: In this article, the refresh address signal from a refresh counter for generating such a refresh address is applied to the random access memory as a burst signal for a predetermined period at predetermined intervals during a display frame time.
15
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