Proceedings Article10.1145/1055137.1055148
Geometric programming for circuit optimization
Stephen Boyd,Seung-Jean Kim +1 more
- 03 Apr 2005
- pp 44-46
TL;DR: This tutorial concerns a method for solving a variety of circuit sizing and optimization problems, which is based on formulating the problem as a geometric program, or a generalized geometric program (GGP).
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Abstract: This tutorial concerns a method for solving a variety of circuit sizing and optimization problems, which is based on formulating the problem as a geometric program (GP), or a generalized geometric program (GGP). These nonlinear, constrained optimization problems can be transformed to convex optimization problems, and then solved (globally) very efficiently.
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Citations
Applications of Artificial Intelligence on the Modeling and Optimization for Analog and Mixed-Signal Circuits: A Review
TL;DR: The basic concepts in AI especially the ones that are more suitable to this application are introduced and the main approaches as well as the pros and cons of each method are discussed.
56
Multi-Objective Optimization of Multi-Level DC–DC Converters Using Geometric Programming
TL;DR: An optimization-oriented method for modeling power converters and their components as posynomial functions is presented, allowing multi-objective optimization of converters to be formulated as a geometric program, a type of convex optimization problem, which allows the use of fast, powerful solvers that guarantee global optimality of solutions.
55
An Efficient Batch Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-objective Acquisition Ensemble
TL;DR: An efficient parallelizable Bayesian optimization algorithm via multiobjective acquisition function ensemble (MACE) to further accelerate the optimization procedure by sampling query points from the Pareto front of the probability of improvement, expected improvement, and lower confidence bound to achieve a delicate tradeoff between exploration and exploitation for the unconstrained optimization problem.
48
Geometric programming for circuit optimization
Stephen Boyd,Seung-Jean Kim +1 more
- 03 Apr 2005
TL;DR: This tutorial concerns a method for solving a variety of circuit sizing and optimization problems, which is based on formulating the problem as a geometric program, or a generalized geometric program (GGP).
A novel heuristic for multi-objective optimization of analog circuit performances
TL;DR: A novel heuristic that deals with generating the Pareto front using the topological properties of the feasible solution space and which does not need optimization background from the user in order to be easily adapted to different applications is presented.
26
References
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Signal Delay in RC Tree Networks
TL;DR: Upper and lower bounds for delay that are computationally simple are presented in this paper and can be used to bound the delay, given the signal threshold, and to certify that a circuit is "fast enough," given both the maximum delay and the voltage threshold.
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Logical Effort: Designing Fast CMOS Circuits
Ivan E. Sutherland,Bob Sproull,David Harris +2 more
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TL;DR: In this article, the authors derived the method of logical effort from design examples and calculated the logical effort of gates, and then calibrated the model to achieve equal rising and falling delays.
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TILOS: A posynomial programming approach to transistor sizing
John P. Fishburn,A. E. Dunlop +1 more
- 01 Jan 2003
TL;DR: A new transistor sizing algorithm, which couples synchronous timing analysis with convex optimization techniques, is presented, which shows that any point found to be locally optimal is certain to be globally optimal.
566
Signal Delay in RC Tree Networks
Paul Penfield,Jorge Rubinstein +1 more
- 29 Jun 1981
TL;DR: Upper and lower bounds for delay that are computationally simple are presented here to certify that a circuit is "fast enough", given both the maximum delay and the voltage threshold.
417