Journal Article10.1109/TCAD.2010.2041846
Functional Test Generation Using Efficient Property Clustering and Learning Techniques
Mingsong Chen,Prabhat Mishra +1 more
57
TL;DR: This paper proposes novel methods to cluster similar properties and develops efficient learning techniques that can significantly reduce the overall test generation time for the properties in a cluster by sharing knowledge across similar test generation instances.
read more
Abstract: Functional verification is one of the major bottlenecks in system-on-chip design due to the combined effects of increasing complexity and lack of automated techniques for generating efficient tests. Several promising ideas using bounded model checking are proposed over the years to efficiently generate counterexamples (tests). The existing researchers have used incremental satisfiability to improve the counterexample generation, involving only one property by sharing knowledge across instances of the same property with incremental bounds. In this paper, we present a framework that can efficiently reduce the overall test generation time by exploiting the similarity among different properties. This paper makes two primary contributions: (1) it proposes novel methods to cluster similar properties; and (2) it develops efficient learning techniques that can significantly reduce the overall test generation time for the properties in a cluster by sharing knowledge across similar test generation instances. Our experimental results using both software and hardware benchmarks demonstrate that our approach can drastically reduce (on average three to five times) the overall test generation time compared to existing methods.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
Post-Silicon Validation in the SoC Era: A Tutorial Introduction
TL;DR: This article provides a comprehensive high-level overview of the various facets of post-silicon validation, and includes industrial case studies illustrating their real-life application.
66
Patent
Integration of data mining and static analysis for hardware design verification
Shobha Vasudevan,David Sheridan,Lingyi Liu +2 more
- 29 Mar 2012
TL;DR: In this paper, a method of generating assertions for verification of a hardware design expressed at a register transfer level (RTL) is presented. Butler et al. use machine learning to generate candidate assertions for variable(s) of interest through machine learning with respect to the domain-specific information.
58
Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution
Alif Ahmed,Farimah Farahmandi,Yousef Iskander,Prabhat Mishra +3 more
- 01 Oct 2018
TL;DR: An automated and scalable test generation approach for activation of hardware Trojans in RTL designs by effective utilization of symbolic execution and concrete simulation and demonstrates that the generated tests are able to activate hard-to-cover Trojan in large and complex RTL benchmarks.
53
SoC Security Verification using Property Checking
Nusrat Farzana,Fahim Rahman,Mark Tehranipoor,Farimah Farahmandi +3 more
- 01 Nov 2019
TL;DR: A property-driven approach to design a secure SoC is proposed with a comprehensive set of reusable and architecture-agnostic properties acting as security-aware design rules and guidelines and develops metrics from these properties to facilitate quantitative security assessment.
51
Automated test generation for Debugging arithmetic circuits
Farimah Farahmandi,Prabhat Mishra +1 more
- 14 Mar 2016
TL;DR: An automated test generation and bug localization technique for debugging arithmetic circuits and a bug detection and correction technique by utilizing the patterns of remainder terms as well as the intersection of regions activated by the generated tests are presented.
39
References
•Book
Computer Architecture: A Quantitative Approach
John L. Hennessy,David A. Patterson +1 more
- 01 Dec 1989
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
12.6K
Chaff: engineering an efficient SAT solver
Matthew W. Moskewicz,Conor F. Madigan,Ying Zhao,Lintao Zhang,Sharad Malik +4 more
- 22 Jun 2001
TL;DR: The development of a new complete solver, Chaff, is described which achieves significant performance gains through careful engineering of all aspects of the search-especially a particularly efficient implementation of Boolean constraint propagation (BCP) and a novel low overhead decision strategy.
Symbolic Model Checking without BDDs
Armin Biere,Alessandro Cimatti,Edmund M. Clarke,Yunshan Zhu +3 more
- 22 Mar 1999
TL;DR: This paper shows how boolean decision procedures, like Stalmarck's Method or the Davis & Putnam Procedure, can replace BDDs, and introduces a bounded model checking procedure for LTL which reduces model checking to propositional satisfiability.
GRASP: a search algorithm for propositional satisfiability
TL;DR: Experimental results obtained from a large number of benchmarks indicate that application of the proposed conflict analysis techniques to SAT algorithms can be extremely effective for aLarge number of representative classes of SAT instances.