Proceedings Article10.1109/SOI.2006.284438
Four-Gate Transistor Voltage-Controlled Negative Differential Resistance Device and Related Circuit Applications
K. Akarvardar,Suheng Chen,J. Vandersand,Benjamin J. Blalock,Ronald D. Schrimpf,B. Prothro,Charles L. Britton,Sorin Cristoloveanu,Paulo Gentil,M.M. Mojarradi +9 more
- 01 Oct 2006
- pp 71-72
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TL;DR: In this article, a voltage-controlled negative differential resistance (NDR) device using SOI four-gate transistors (G4-FETs) is presented, and an innovative LC oscillator and Schmitt trigger circuits based on the G4 FET NDR device are experimentally demonstrated.
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Abstract: A novel voltage-controlled negative differential resistance device, using complementary SOI Four-Gate Transistors (G4-FETs) is presented Innovative LC oscillator and Schmitt trigger circuits based on the G4-FET NDR device are experimentally demonstrated
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Citations
Depletion-All-Around Operation of the SOI Four-Gate Transistor
TL;DR: The depletion-all-around (DAA) as discussed by the authors enables majority carriers to flow in the volume of the silicon film far from the silicon/oxide interfaces, which leads to excellent analog performance, low noise, and reduced sensitivity to ionizing radiation.
53
Electronic Circuit with Controllable Negative Differential Resistance and its Applications
TL;DR: In this article, a new NDR circuit that comprises a combination of a field effect transistor (FET) and a simple bipolar junction transistor (BJT) current mirror (CM) with multiple outputs is proposed.
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Modeling of SOI four-gate transistor (G4FET) using multidimensional spline interpolation method
TL;DR: A numerical multidimensional spline interpolation method for CAD implementation of silicon-on-insulator (SOI) four-gate transistors (G 4 FET) is presented and shown to work very well when independent variables do not exceed the range of training data set used for the model development.
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Design of an Enhanced Reconfigurable Chaotic Oscillator using G 4 FET-NDR Based Discrete Map
Sakib Hasan,Aysha S. Shanta,Partha Sarathi Paul,Maisha Sadia,Badruddoja Majumder,Garrett S. Rose +5 more
- 15 Nov 2020
TL;DR: A novel chaotic map is introduced using a voltage controlled negative differential resistance (NDR) circuit composed of an n-channel and a p-channel silicon-on-insulator (SOI) four-gate transistor to create a discrete chaotic map with three bifurcation parameters.
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Numerical modeling and implementation in circuit simulator of SOI four-gate transistor (G4FET) using multidimensional Lagrange and Bernstein polynomial
TL;DR: Two efficient numerical models developed for simulating circuits containing silicon-on-insulator four-gate transistors (G4FET) provide a single multivariate polynomial expression that is valid across different biasing regimes as long as it falls within the range of data set used to develop the model.
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References
Investigation of the four-gate action in G/sup 4/-FETs
B. Dufrene,K. Akarvardar,Sorin Cristoloveanu,Benjamin J. Blalock,R. Gentil,Elzbieta Kolawa,M.M. Mojarradi +6 more
TL;DR: In this article, the four-gate silicon-on-insulator transistor (G/sup 4/FET) combines MOS and JFET actions in a single transistor to control the drain current.
67
A ternary Schmitt trigger
K. Ramkumar,K. Nagaraj +1 more
TL;DR: A new ternARY circuit, namely, a ternary Schmitt trigger, is presented, which is suitable for integration using CMOS technology and offers a high degree of design flexibility.
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