Patent
Floating point microprocessor with directable two level microinstructions
Tich Dao,Gary R. Burke +1 more
- 28 Aug 1986
169
TL;DR: In this paper, a microprocessor integrator circuit includes split nanocode memories which enable simultaneous execution of an arithmetic operation and an operand fetch for maximizing throughput for maximizing throughput.
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Abstract: A microprocessor integrator circuit includes split nanocode memories which enables simultaneous execution of an arithmetic operation and an operand fetch for maximizing through-put. The circuit also includes a shared sequencing arithmetic logic unit which handles all microcode sequencing plus memory address sequencing. The circuit also provides nanocode sequencing which enables storage of constants and data in a microcode space which can include an off-chip writable control store. In addition, two level microcode is utilized to enable long routines to be vertically encoded without the overhead of a large number of read only memory outputs.
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Citations
Patent
Alignment and ordering of vector elements for single instruction multiple data processing
Timothy J. Van Hook,Peter Yan-Tek Hsu,William A. Huffman,Henry Packard Moreton,Earl A. Killian +4 more
- 06 Feb 2007
TL;DR: In this paper, the alignment and ordering of vector elements for SIMD processing is described, and a starting byte specifying the first byte of an aligned vector is determined, and then a vector is extracted from the first register and the second register, and replicated into the elements in the third register in a particular order suitable for subsequent SIMD vector processing.
251
Patent
High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations
David B. Witt,William M. Johnson +1 more
- 10 Jul 1995
TL;DR: In this article, the superscalar microprocessor is presented, which includes an integer functional unit and a floating-point functional unit that share a high performance main data processing bus.
195
Patent
Microcode patch device and method for patching microcode using match registers and patch routines
Kevin J. McGrath,James K. Pickett +1 more
- 27 Oct 1999
TL;DR: In this article, a random access memory (RAM) is provided in a processor for implementing microcode patches, which is part of the normal microcode contained in a microcode read only memory (ROM) unit of the processor.
161
Patent
Dependency checking and forwarding of variable width operands
Gerald D. Zuraski,Scott A. White,Murali S Chinnakonda,David S. Christie +3 more
- 26 Apr 1994
TL;DR: In this article, a pipelined or superscalar processor that executes operations utilizing operand data of variable bit widths improves parallel performance by partitioning a fixed bit width operand into several partial operand fields (215, 216 and 217) and checking for data dependencies, tagging and forwarding data in these fields independently of one another.
108
Patent
Dependency table for reducing dependency checking hardware
Muralidharan S. Chinnakonda,Thang M. Tran,Wade A. Walker +2 more
- 05 May 2000
TL;DR: In this article, a dependency table stores a reorder buffer tag for each register, which corresponds to the last of the instructions within the Reorder buffer (in program order) to update the register.
105
References
A numeric data processor
TL;DR: A 4-state HMOS ROM, with nearly 700 bits of RAM for an internal stack and 29,000 bits of ROM for microcode and constants for a math processor, will be described.
148
The Organization of Microprogram Stores
TL;DR: Some aspects of control store archi tectures are surveyed, including the organization of microinst ruct ion words, and the effects of different t iming schemes on the complexi ty of both control s tore and hos t mach ine organizat ions.
77
Patent
Data processing system having two levels of program control
J Liebel
- 28 Apr 1972
TL;DR: In this paper, a data processing system comprising a local storage means for storing information to be processed and operation means connected to the local storage mean for performing operations, such as arithmetic and logical, on information supplied thereto.
76
Patent
Sharing of microprograms between processors
George S Hoff,Richard P. Kelly +1 more
- 13 Aug 1970
TL;DR: In this article, two microprogrammable control elements of both processors are interconnected to permit the fixed word processor to share microprograms of the variable length processor for executing instructions not included in its repertoire.
71
Patent
Numerical control system with downloading capability
Ronald J. Toke,William A. Donze +1 more
- 14 Nov 1977
TL;DR: In this paper, a numerical control system which employs a programmed numerical control processor to perform the numerical control functions is coupled to a bulk storage device by a host computer, which stores a download library which includes not only part programs, but also system software programs and diagnostic programs.
66