Fault diagnosis and logic debugging using Boolean satisfiability

Question

1. What contributions have the authors mentioned in the paper "Fault diagnosis and logic debugging using boolean satisfiability" ?

2. What techniques can be used to improve performance of a SAT solver?

3. What is the reason why the SAT solver may become large?

4. How many multiplexers can be used to convert a netlist?

Accepted Answer

This work proposes a novel Boolean satisfiability-based method for multiple-fault diagnosis and multiple-design-error diagnosis in combinational and sequential circuits.. They also suggest that satisfiability captures significant characteristics of the problem of diagnosis and encourage novel research in satisfiability-based diagnosis as a complementary process to design verification.

Accepted Answer

Performance is improved by taking advantage of backtracking and clause-learning [2], [10], [11] techniques in modern SAT solvers.

Accepted Answer

Since the CNF of the circuit presented to the SAT solver is replicated for a number of cycles for each input/outputvector sequence, the SAT instance may become large.

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The resulting netlist can be turned into a CNF formula with O(n) clauses [7], since each multiplexer can be translated to CNF using four clauses.

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Simulation-based algorithms [20], [25], [26] typically use a backtrace procedure to identify potential fault locations, and then perform simulation to verify that a candidate location is capable of correcting the design or explaining the fault.

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The solver performs these operations implicitly using the learning and conflictanalysis procedures built into modern SAT engines.

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3. In other words, instead of running the SAT solver on the original formula ΦS , the authors can run it in consecutive passes on formulas ΦiS , 1 ≤ i ≤ k/p .

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Since creating the CNF clauses contributes a constant multiplicative factor of 14, the size of the CNF formula for the counter is O(n).

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In diagnosis of combinational circuits, the authors use a total of 20 erroneous input test vectors (|VC| = 20) and the algorithm runs in four passes of five vectors each (Heuristic 1, Section V-A).

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The authors encode constraints that enumerate the same solutions space, but the authors do so implicitly by using the hardware construction shown in Fig. 5(a), which is converted into CNF and appended to ΦC .

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The authors believe that this is because the sequential-diagnosis SAT-based instances, as formulated herein, are SAT problems in which solution constraints are tightly specified in terms of the circuit structure and input test sequences.

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Assume that the binary representation of the integer passed from the adder to the comparator is blog n . . . b1b0. A comparator for SAT-based debugging of two faults is formed by adding CNF blog n · blog n−1 · . . . · b2 · b1 · b0 to EN (S).

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The authors can replicate this effect in ΦC simply by generating a single wi input for line li and sharing it among all multiplexed copies of the circuit.

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The algorithms for combinational and sequential diagnosis are described on circuits with r primary inputs X = (x1, x2, . . . , xr) and t primary outputs Y = (y1, y2, . . . , yt) = f(X).

Accepted Answer

To ease the task of the SAT solver, test sequences can be sorted in increasing order of size mi1 ≤ mi2 ≤ · · · ≤ mik , and presented in this order to the SAT solver.

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In order to simplify the presentation, the authors develop the theoretical problem formulation around an example that assumes a single-input sequence V 1,m1 with two cycles; that is, k = 1 and m1 = 2.

Fault diagnosis and logic debugging using Boolean satisfiability

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Most frequently asked questions

1. What contributions have the authors mentioned in the paper "Fault diagnosis and logic debugging using boolean satisfiability" ?

2. What techniques can be used to improve performance of a SAT solver?

3. What is the reason why the SAT solver may become large?

4. How many multiplexers can be used to convert a netlist?

5. What is the common method of determining fault locations?

6. How does the solver perform these operations?

7. How can the authors run the SAT solver on the original formula?

8. What is the size of the CNF formula for the counter?

9. How many passes of each vector are used?

10. How do the authors encode constraints that enumerate the same solutions space?

11. Why do the authors believe that the SAT solver makes few “wrong” decisions?

12. What is the binary representation of the integer passed from the adder to the comparator?

13. How can the authors replicate this effect in C?

14. What is the algorithm for combinational and sequential diagnosis?

15. How can a SAT solver be sorted?

16. What is the theoretical problem formulation for a single input sequence?

Figures

Citations

QBF-Based Formal Verification: Experience and Perspectives

Diagnosis of discrete-event systems using satisfiability algorithms

A novel SAT-based approach to model based diagnosis

Post-silicon fault localisation using maximum satisfiability and backbones

Approximate Model-Based Diagnosis Using Greedy Stochastic Search

References

Chaff: engineering an efficient SAT solver

Digital Systems Testing and Testable Design

GRASP: a search algorithm for propositional satisfiability

Logic design verification via test generation

FPGA routing and routability estimation via Boolean satisfiability

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