Journal Article10.1109/tcad.2022.3221694
Fast Surrogate-assisted Constrained Multi-objective Optimization for Analog Circuit Sizing via Self-adaptive Incremental Learning
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TL;DR: In this article , an efficient surrogate-assisted constrained multi-objective evolutionary algorithm for analog circuit sizing via self-adaptive incremental learning is proposed, which reduces the total optimization time in four aspects: by reusing the previously trained models, the incremental learning technique is introduced to reduce the time complexity of training the Kriging model from O(n3) to O (n2), where n is the number of training points.
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Abstract: In this paper, we propose an efficient surrogate-assisted constrained multi-objective evolutionary algorithm for analog circuit sizing via self-adaptive incremental learning. The proposed approach reduces the total optimization time in four aspects. First, by reusing the previously trained models, the incremental learning technique is introduced to reduce the time complexity of training the Kriging model from O(n3) to O(n2), where n is the number of training points. Second, a self-adaptive strategy to control when to update hyperparameters is proposed to further reduce the training time of the Kriging model. Third, our method is driven by prescreening the most promising population instead of internal optimization which saves the prediction time of the Kriging model. Fourth, the maximin distance-based expected improvement matrix criterion is introduced as the acquisition function to formulate multiple objectives into a scalar function, reducing the sorting time to rank population. Experimental results on three real-world circuits demonstrate that compared with the state-of-the-art multi-objective Bayesian optimization, our method achieves a speedup of up to 13× in total runtime without surrendering optimization results. To be more specific, our method reduces the training time of Kriging model by 96%, the prediction time by 99% and the sorting time to rank population by up to 92%. Compared with NSGA-II, there is up to 6× speedup in terms of the total runtime with better results.
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Citations
Knowledge Transfer Framework for PVT Robustness in Analog Integrated Circuits
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