Journal Article10.1109/43.494701
Fast factorization method for implicit cube set representation
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TL;DR: This paper presents a fast weak-division method for implicit cube set representation using Zero-Suppressed Binary Decision Diagrams, which are a new type of Binary decision Diagram adapted for representing sets of combinations.
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Abstract: This paper presents a fast weak-division method for implicit cube set representation using Zero-Suppressed Binary Decision Diagrams, which are a new type of Binary Decision Diagram adapted for representing sets of combinations. Our new weak-division algorithm can be executed in a time almost proportional to the size of the graph, regardless of the number of cubes and literals. Based on this technique, we implemented a simple program for optimizing multilevel logic circuits. Experimental results indicate that we can quickly flatten and factorize multilevel logics even for parity functions and full adders, which have never been flattened in other methods. Our method greatly accelerates multilevel logic synthesis systems and enlarges the scale of applicable circuits.
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Citations
Translating Pseudo-Boolean Constraints into SAT
Niklas Een,Niklas Sörensson +1 more
TL;DR: By applying a proper mix of translation techniques, a SAT-solver can perform on a par with the best existing native pseudo-boolean solvers, particularly valuable in cases where the constraint problem of interest is naturally expressed as a SAT problem, except for a handful of constraints.
BDS: a BDD-based logic optimization system
Congguang Yang,Maciej Ciesielski +1 more
TL;DR: The experimental results show that BDD-based logic decomposition is a promising alternative to the existing logic optimization approaches, and offers a superior runtime advantage over traditional logic synthesis systems.
BDS: a BDD-based logic optimization system
Congguang Yang,Maciej Ciesielski,Vigyan Singhal +2 more
- 01 Jun 2000
TL;DR: The experimental results show that BDS has a capability to handle very large circuits, and offers a superior runtime advantage over SIS, with comparable results in terms of circuit area and often improved delay.
181
Decision Diagrams and Pass Transistor Logic Synthesis
Valeria Bertacco,Shin-ichi Minato,P. Verplaetse,Luca Benini,and G. D Micheli +4 more
- 01 Dec 1997
TL;DR: This work presents methods for the automatic generation of macro-cells using pass transistors and domino logic based on BDD and Z BDD representations of the logic functions, and shows that the macro- cells perform well up to a certain complexity of the Logic function.
Logic optimization by output phase assignment in dynamic logic synthesis
Ruchir Puri,Andrew Augustus Bjorksten,Thomas Edward Rosser +2 more
- 10 Nov 1996
TL;DR: This paper presents this previously unaddressed problem of output phase assignment for minimum area duplication in dynamic logic synthesis and gives both optimal and heuristic algorithms for minimizing logic duplication.
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Shin-ichi Minato
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ESPRESSO-SIGNATURE: A New Exact Minimizer for Logic Functions
Patrick C. McGeer,Jagesh V. Sanghavi,Robert K. Brayton,Alberto Sangiovanni Vincentelli +3 more
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TL;DR: A new algorithm for exact two-level logic optimization which radically improves the Quine-McCluskey (QM) procedure and improves on the runtime and memory usage of ESPRESSO-EXACT by average factors of 1.78 and 1.19.
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