Fast Boolean optimization by rewiring
Shih-Chieh Chang,Lukas P. P. P. van Ginneken,Malgorzata Marek-Sadowska +2 more
- 01 Nov 1996
- pp 262-269
TL;DR: The algorithm applies the reasoning of Automatic Test Pattern Generation (ATPG) which can detect redundancy efficiently and analyzes different characteristics of mandatory assignments during the ATPG process to find the most efficient Boolean logic optimization method.
read more
Abstract: This paper presents a very efficient Boolean logic optimization method. The boolean optimization is achieved by adding and removing redundant wires in a circuit. Our algorithm applies the reasoning of Automatic Test Pattern Generation (ATPG) which can detect redundancy efficiently. During the ATPG process, mandatory assignments are assignments which must be satisfied. Our algorithm analyzes different characteristics of mandatory assignments during the ATPG process. New theoretical results based on the analysis are presented which lead to significant performance improvements. The fast run time and the excellent scaling to large problems make our Boolean optimization method practical for industrial applications. Experiments show that the optimization results are comparable to those of Kunz and Pradhan (1994) while the run time is two orders of magnitude faster (average 126/spl times/ speed up). Furthermore, we report optimization results for several large examples, which were previously thought to be too large to be handled by Boolean optimization methods.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
Circuit optimization by rewiring
TL;DR: This work presents a very efficient optimization method suitable for multi-level combinational circuits based on incremental restructuring of a circuit through a sequence of additions and removals of redundant wires to eliminate unnecessary wire redundancy checking.
77
Implicit enumeration of structural changes in circuit optimization
Victor N. Kravets,Prabhakar Kudva +1 more
- 07 Jun 2004
TL;DR: The restructuring technique relies on the symbolic statements of functional decomposition which explores behavioral equivalence of circuit signals through rewiring and resubstitution to obtain much improved delays of the already optimized circuits along with their area savings.
38
Single-pass redundancy addition and removal
Chih Wei Jim Chang,Malgorzata Marek-Sadowska +1 more
- 04 Nov 2001
TL;DR: This paper proposes a new reasoning scheme which directly identifies alternative wires without performing trial-and-error redundancy tests and shows up to 15 times speedup in comparison to the best techniques in literature.
38
A fast graph-based alternative wiring scheme for Boolean networks
Yu-Liang Wu,Wangning Long,Hongbing Fan +2 more
- 04 Jan 2000
TL;DR: This paper studies the approach of applying purely graph based local pattern search methods in locating alternative wires by a simple coupling with the SIS algebraic operations and shows that this scheme is very fast and has the advantage of searching both the nearby forward and backward alternative wires easily.
27
•Journal Article
A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks
TL;DR: In this article, a graph-based local pattern search method was proposed to find alternative wires in a graph. But the method is limited to 2 edges distant from the target wire.
26
References
•Book
Digital Systems Testing and Testable Design
Miron Abramovici,M.A. Breuer,Arthur D. Friedman +2 more
- 01 Jan 1990
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
2.9K
Advanced automatic t est pattern g eneration and redundancy identification techniques
Michael H. Schulz,Elisabeth Auth +1 more
- 01 Jan 1988
TL;DR: An improved implication procedure and an improved unique sensitization procedure significantly advance the deterministic test pattern generation and redundancy identification especially for those faults, for which it is difficult to generate a test pattern or to prove them to be redundant, respectively.
163
Advanced automatic test pattern generation and redundancy identification techniques
M.H. Schulz,E. Auth +1 more
- 27 Jun 1988
TL;DR: Based on the sophisticated strategies used in the automatic test pattern generation system SOCRATES, this article presented several concepts aiming at a further improvement and acceleration of the deterministic test pattern generator and redundancy identification process.
160
Perturb and simplify: multilevel Boolean network optimizer
TL;DR: This paper presents logic optimization techniques for multilevel combinational networks which apply a sequence of perturbations which result in simplification of the circuit through wires/gates addition and removal which are guided by the ATPG based reasoning.
143
Multi-level logic optimization by implication analysis
Wolfgang Kunz,Prem R. Menon +1 more
- 06 Nov 1994
TL;DR: It is shown that Recursive Learning can derive “good” Boolean divisors justifying the effort to attempt a Boolean division, and for 9 out of 10 ISCAS-85 benchmark circuits, the tool HANNIBAL obtains smaller circuits than the well-known synthesis system SIS.
119
Related Papers (5)
Kwang-Ting Cheng,Luis Entrena +1 more
- 22 Feb 1993
Shih-Chieh Chang,Malgorzata Marek-Sadowska +1 more
- 06 Nov 1994