Proceedings Article10.1109/MWSCAS.2011.6026486
Exploring energy-efficient DRAM array organizations
Seongil O,Sungwoo Choo,Jung Ho Ahn +2 more
- 23 Sep 2011
- pp 1-4
8
TL;DR: This paper compares various mainmemory DRAM array organizations using multithreaded and multiprogrammed workloads on a chip-multiprocessor system with die-stacked DRAM memory in search of energy-efficient array configurations.
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Abstract: DRAM is widely used as main-memory storage in contemporary computer systems. As VLSI process technology advances, more transistors can be integrated in a single die leading to higher storage capacity and communication throughput per DRAM chip. New DRAM standards are created in order to keep up with these trends, and many factors such as performance, energy efficiency, reliability, and fabrication/testing cost are considered when a new DRAM architecture is designed. However, there are few studies on DRAM array organizations that consider both performance and energy efficiency of entire computer systems using the organizations. In this paper, we explore the design space of contemporary DRAM array organizations by varying the number of pages that can be concurrently accessed and the size of the pages. We compare various mainmemory DRAM array organizations using multithreaded and multiprogrammed workloads on a chip-multiprocessor system with die-stacked DRAM memory in search of energy-efficient array configurations.
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Citations
Patent
System, method, and computer program product for improving memory systems
Michael S Smith
- 10 Dec 2012
TL;DR: In this paper, a system, method, and computer program product for a memory system is described, which includes a first semiconductor platform including at least one first circuit, and at least two additional semiconductor platforms stacked with the first and additional circuits.
387
A survey of architectural techniques for DRAM power management
TL;DR: The aim of this paper is to equip the engineers and architects with knowledge of the state of the art DRAM power saving techniques and motivate them to design novel solutions for addressing the challenges presented by the memory power wall problem.
Exploration and Optimization of 3-D Integrated DRAM Subsystems
TL;DR: This paper proposes a highly energy-efficient DRAM subsystem for next-generation 3-D-integrated SoCs, consisting of a SDR/DDR 3- D-DRAM controller and an attached 3-Ds-stacked DRAM cube with fine-grained access and a flexible (WIDE-IO) interface.
45
DArT: A component-based DRAM area, power, and timing modeling tool
Hsiu Chuan Shih,Pei-Wen Luo,Jen-Chieh Yeh,Shu-Yen Lin,Ding-Ming Kwai,Shih Lien Lu,Andre Schaefer,Cheng-Wen Wu +7 more
TL;DR: DRAM area power timing (DArT), a DRAM area, power, and timing modeling tool, for array assembly and interface customization is presented, providing increased flexibility and higher accuracy, making DArT suitable for DRAM architecture exploration and performance estimation.
17
Computational Process Optimization of Array Edges
Bernd Küchler,Artem Shamsuarov,Thomas Mülders,Ulrich Klostermann,Seung-Hune Yang,Seongho Moon,Vitaliy Domnenko,Sung-Woon Park +7 more
TL;DR: This paper focuses on how to optimize the DRAM array edge automatically in contrast to manual optimization approaches that were used effectively but at high cost, and shows how to squeeze out the masks degrees of freedom to stay within tight pattern tolerances.
6
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