Journal Article10.1109/L-CA.2002.4
Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example
TL;DR: This work designs a loop cache specifically with tuning in mind, showing a 70% reduction in instruction memory access, for MIPS and 8051 processors – representing twice the reduction from a regular loop cache, translating to good power savings.
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Abstract: Embedded systems commonly execute oneprogram for their lifetime. Designing embedded systemarchitectures with configurable components, such thatthose components can be tuned to that one program basedon a program pre-analysis, can yield significant powerand performance benefits. We illustrate such benefits bydesigning a loop cache specifically with tuning in mind.Our results show a 70% reduction in instruction memoryaccess, for MIPS and 8051 processors representingtwice the reduction from a regular loop cache, translatingto good power savings.
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Citations
Cache-aware scratchpad allocation algorithm
Manish Verma,Lars Wehmeyer,Peter Marwedel +2 more
- 16 Feb 2004
TL;DR: This work uses the scratchpad for storing instructions and proposes a generic cache aware scratchpad allocation (CASA) algorithm, which results in an average reduction of 8-29% in instruction memory energy consumption compared to a previously published technique for benchmarks from the mediabench suite.
133
A dynamic code placement technique for scratchpad memory using postpass optimization
Bernhard Egger,Chihun Kim,Choonki Jang,Yoonsung Nam,Jaejin Lee,Sang Lyul Min +5 more
- 22 Oct 2006
TL;DR: A fully automatic dynamic scratch-pad memory (SPM) management technique for instructions that loads required code segments into the SPM on demand at runtime based on postpass analysis and optimization techniques, and it handles the whole program, including libraries.
Fast, predictable and low energy memory references through architecture-aware compilation
Peter Marwedel,Lars Wehmeyer,Manish Verma,Stefan Steinke,Urs Helmig +4 more
- 27 Jan 2004
TL;DR: A comprehensive set of algorithms that can be applied at design time in order to maximally exploit scratch pad memories (SPMs) are described, showing that both the energy consumption as well as the computed worst case execution time (WCET) can be reduced by up to to 80% and 48%, respectively, by establishing a strong link between the memory architecture and the compiler.
38
Scratchpad Memory Management Techniques for Code in Embedded Systems without an MMU
TL;DR: A code scratchpad memory (SPM) management technique with demand paging for embedded systems that have no memory management unit is proposed and results show both a runtime performance improvement and a reduction of the energy consumption.
34
New decompilation techniques for binary-level co-processor generation
G. Stiff,Frank Vahid +1 more
- 31 May 2005
TL;DR: Two new decompilation techniques, strength promotion and loop rerolling, are introduced and shown that they are necessary to synthesize an efficient custom hardware coprocessor from a binary in the presence of software compiler optimizations, and the robustness of binary-level co-processor generation is shown.
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Joseph A. Fisher
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TL;DR: It is argued in this paper that architectural variety will soon again become an important topic, with the major motivation being increased performance due to the customization of CPUs to their intended use.
Low-Cost Embedded Program Loop Caching - Revisited
Lea Hwang Lee,Bill Moyer,John H. Arends +2 more
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TL;DR: The modified loop caching scheme proposed in this paper is capable of capturing only part of the program loop without having any cache conflict problem, and can reduce instruction fetch energy more than other loop cache schemes previously proposed.
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Lea Hwang Lee,Bill Moyer,John H. Arends +2 more
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TL;DR: This paper proposes using a small instruction buffer, also called a loop cache, to save power in caches, which has no address tag store and knows precisely whether the next instruction request will hit in the loop cache well ahead of time.