Execution cost interval refinement in static software analysis

TL;DR: A measurement based approach to estimate the worst case execution time on a fully featured processor, suitable for processors equipped with advanced acceleration techniques, and an existing extreme value statistic approach is extended, to handle combinations of measurements.

TL;DR: By analyzing the control flow graph the compiler uses for optimization, systematic information on how the code has to be measured can be gained and the code can be automatically instrumented and measured to bound the execution time of the real time tasks.

TL;DR: An approach to analysis of process behavior using running time intervals is presented, which improves previous work by exploiting program segments with single paths and by taking the execution context into account and shows the superiority of the presented approach over well-established approaches.

TL;DR: This paper presents an approach to analysis of process behavior using intervals, which improves previous work by exploiting program segments with single paths and by taking the execution context into account.

TL;DR: This book discusses the design of a Code Generator, the role of the Lexical Analyzer, and other topics related to code generation and optimization.

TL;DR: This custom VLSI implementation of a microprocessor architecture delivers 184 Drystone/MIPS at 162 MHz dissipating 0.5 W using an 1.5 V internal supply and Clock generation uses an on-chip PLL with 3.68 MHz input clock to minimize high frequency clock signals on the board.

TL;DR: A 160 MHz 500 mW 32 b StrongARM(R) microprocessor designed for low-power, low-cost applications that implements the ARM(R) V4 instruction set and is bus compatible with earlier implementations is described.