Evaluating Statistical Power Optimization
Jason Cong,Puneet Gupta,J Lee +2 more
TL;DR: This paper quantifies the difference between the statistical and deterministic optima of leakage power while making no assumptions about the delay model, and develops a framework for deriving a theoretical upper bound on the suboptimality that is incurred by using the deterministic optimum as an approximation for the statistical optimum.
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Abstract: In response to the increasing variations in integrated-circuit manufacturing, the current trend is to create designs that take these variations into account statistically. In this paper, we quantify the difference between the statistical and deterministic optima of leakage power while making no assumptions about the delay model. We develop a framework for deriving a theoretical upper bound on the suboptimality that is incurred by using the deterministic optimum as an approximation for the statistical optimum. We show that for the mean power measure, the deterministic optima is an excellent approximation, and for the mean plus standard deviation measures, the optimality gap increases as the amount of inter-die variation grows, for a suite of benchmark circuits in a 45 nm technology. For large variations, we show that there are excellent linear approximations that can be used to approximate the effects of variation. Therefore, the need to develop special statistical power optimization algorithms is questionable.
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Citations
•Book
IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society
Ieee Circuits
- 01 Jan 1982
TL;DR: Manuscripts focusing on methods, algorithms, and human-machine interfaces for physical and logical design of integrated-circuit and systems designs of all complexities and practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.
730
Hardware Trojan detection based on correlated path delays in defiance of variations with spatial correlations
Fatma Nur Esirci,Alp Arslan Bayrakci +1 more
- 27 Mar 2017
TL;DR: A method that smartly selects two highly correlated paths for each interconnect (edge) that is suspected to have an HT on it that enables the detection of even the minimally invasive Trojans in spite of both inter and intra die variations with the spatial correlations.
16
•Book
Discrete Circuit Optimization
John G. Lee,Puneet Gupta +1 more
- 19 Mar 2012
TL;DR: The discrete gate sizing and threshold assignment problem has attracted significant research attention over the past three decades as mentioned in this paper, and a survey of the literature can be found in Section 2.1.
Stochastic logical effort as a variation aware delay model to estimate timing yield
TL;DR: The results demonstrate that the approximate SLE model can capture the delay variations and ISLE achieves the same accuracy as the standard Monte Carlo estimator with a cost reduction of about 180×on the average for ISCAS'85 benchmark circuits.
6
Delay based hardware Trojan detection exploiting spatial correlations to suppress variations
TL;DR: In this article , a non-invasive, golden chip free delay based hardware Trojan detection method is proposed, which exploits the inherent spatial correlations to suppress the Trojan hiding effect of the variations.
3
References
A new measure of rank correlation
TL;DR: Rank correlation as mentioned in this paper is a measure of similarity between two rankings of the same set of individuals, and it has been used in psychological work to compare two different rankings of individuals in order to indicate similarity of taste.
6.8K
•Book
IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society
Ieee Circuits
- 01 Jan 1982
TL;DR: Manuscripts focusing on methods, algorithms, and human-machine interfaces for physical and logical design of integrated-circuit and systems designs of all complexities and practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.
730
Statistical analysis of subthreshold leakage current for VLSI circuits
TL;DR: An analytical expression is derived to estimate the probability density function of the leakage current for stacked devices found in CMOS gates and an approach is presented to account for both the inter- and intra-die gate length variations to ensure that the circuit leakage PDF correctly models both types of variation.
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
Ashish Srivastava,Dennis Sylvester,David Blaauw +2 more
- 07 Jun 2004
TL;DR: In this article, the authors proposed a new statistically aware dual-Vt and sizing optimization that considers both the variability in performance and leakage of a design, and demonstrated that using this statistically aware optimization, leakage power can be reduced by 15-35% compared to traditional deterministic analysis.
144
Robust gate sizing by geometric programming
Jaskirat Singh,Vidyasagar Nookala,Zhi-Quan Luo,Sachin S. Sapatnekar +3 more
- 13 Jun 2005
TL;DR: The robust gate sizing solution having the same area has fewer timing violations and the timing yield of the robustly optimized circuits improves manifold over the traditional deterministically sized circuits.