Patent
Error correction circuit
Yasuharu Tomimitsu
- 28 Jan 1988
16
TL;DR: An error correction circuit comprises a plurality of Galois body operation units coupled in cascade through a bus but operated in parallel as discussed by the authors, each of the units includes a Galois BCH multiplication and addition circuits.
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Abstract: An error correction circuit comprises a plurality of Galois body operation units coupled in cascade through a bus but operated in parallel. Each of the units includes a Galois body multiplication circuit, a Galois body addition circuit and a plurality of registers, thereby generating and decoding a BCH code.
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Citations
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Error-correcting encoder, error-correcting decoder and data transmitting system with error-correcting codes
Yasuyuki Sakai,Hideo Yoshida,Toshio Tokita +2 more
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Implementations of AES algorithm for reducing hardware with improved efficiency
Kouhei Nadehara
- 27 Jan 2004
TL;DR: In this paper, an AES encryption processor is provided for reducing hardware with improved throughput, which is composed of a selector unit selecting an element of a state in response to row and column indices.
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Method for testing ECC logic
Ronald Xavier Arroyo,William E. Burky,Tricia A. Gruwell,Joaquin Hinojosa +3 more
- 20 Sep 1993
TL;DR: In this paper, a method for checking the test logic contained in a computer memory system during POST such that any errors can be determined and made available to the system software prior to beginning processing operations is presented.
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Error-correcting method and decoder using the same
Tohru Inoue
- 05 Feb 1993
TL;DR: In this article, the Reed-Solomon code and the BCH code are used for correcting errors in a GF(2m) system with a buffer memory of m×L(L≧1)×N.
27
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Multiplexing output from second execution unit add/saturation processing portion of wider width intermediate result of first primitive execution unit for compound computation
Harry Barowski,J. Adam Butts,Stephen V. Kosonocky,Silvia Melitta Mueller,Jochen Preiss +4 more
- 31 Jan 2008
TL;DR: In this paper, a method for executing multiple computational primitives is provided in accordance with exemplary embodiments, where a first computational unit and at least a second computational unit cooperate to execute multiple computations.
18
References
Patent
Error correcting system
Masahide Nagumo,June Inagawa,Kojima Tadashi +2 more
- 15 Oct 1982
TL;DR: In this paper, double correction BCH codes are used to generate error locations σ1 and σ2 and error patterns e, and e2, respectively, using the elements of the Galois field GF(2m).
40
Patent
Method and means for error detection and correction in high speed data transmission codes
Todd Citron,Thomas Kailath +1 more
- 15 Feb 1984
TL;DR: A method and processing matrix for detection and correction of errors in coded data based on determining the error location and error evaluator polynomials using the relationship defined by the key equation is presented in this article.
32
Patent
Method and apparatus for translating a predetermined Hamming code to an expanded class of Hamming codes
Edgar R. Goodrich,Philip Navratil +1 more
- 04 Apr 1983
TL;DR: In this article, an error checking and correcting (ECC) system implemented in large scale integration (LSI) form having a predetermined Hamming code checks the accuracy of data and corrects the data via check bits.
4
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