Patent
Error correction chip for memory applications
Mirmajid Seyyedy
- 29 Jan 1997
74
TL;DR: In this article, a memory module, such as a SIMM or DIMM, is provided which incorporates error correction circuitry, which identifies and corrects errors in communications between the memory module and an external processor.
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Abstract: A memory module, such as a SIMM or DIMM, is provided which incorporates error correction circuitry. The error correction circuitry identifies and corrects errors in communications between the memory module and an external processor. A reliable data processing system is also provided, incorporating the memory module comprising the error correction circuitry with a processor. The yield of manufactured chips is increased by presorting the memory chips which make up the memory module, such that a chip with one or more defective cells may be included in a memory module so long as no other chip has defective cells at the same location.
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Citations
Patent
High reliability memory module with a fault tolerant address and command bus
Kevin C. Gower,Bruce G. Hazelzet,Mark W. Kellogg,David J. Perlman +3 more
- 20 Apr 2006
TL;DR: In this article, a high reliability dual-inline memory module with a fault tolerant address and command bus for use in a server is presented. But the memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a DRAM, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and
220
Patent
Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM)
Lee A. Burton
- 06 Aug 2007
TL;DR: In this article, an enhanced switch/network adapter port incorporating shared memory resources (SNAPM™) selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module (FB-DIMM) format for clustered computing systems employing direct-execution logic such as multi-adaptive processor elements (MAP®).
186
Patent
Stacked DRAM memory chip for a dual inline memory module (DIMM)
Siva Raghuram
- 10 Dec 2004
TL;DR: In this paper, a DRAM Memory Chip for a Dual In Line Memory Module (DIMM) having a predetermined number (M) of stacked DRAM memory dies is described.
161
Patent
Variable strength ECC
William H. Radke
- 31 Aug 2006
TL;DR: In this paper, the authors describe data detection and correction in memory controllers, memory systems, and/or non-volatile memory devices by allowing the number of ECC check bytes being utilized to be varied to increase or decrease the ECC coverage.
128
Patent
Error detection/correction code which detects and corrects component failure and which provides single bit error correction subsequent to component failure
Robert E. Cypher
- 28 Jun 2002
TL;DR: In this paper, a memory controller comprises a check bit encoder circuit and a check/correct circuit, which are coupled to decode the encoded data block and perform at least the detection of (i) and (ii) on the data block.
120
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Patent
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Eliyahou Harari,Robert D. Norman,Sanjay Mehrotra +2 more
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TL;DR: In this paper, the authors proposed selective multiple sector erase, in which any combinations of Flash sectors may be erased together, and select sectors among the selected combination may also be de-selected during the erase operation.
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292
Patent
Write reduction in flash memory systems through ECC usage
Robert D. Norman
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TL;DR: In this article, error correction code (ECC) circuitry receives the first set of data and calculates first ECC check bits representative of the first data, and then compares the first check bits with second check bits representing a second set of stored data stored in the array to generate an ECC comparison signal.
251
Patent
Directly bonded simm module
Tim J. Corbett,Alan G. Wood +1 more
- 15 Feb 1989
TL;DR: A leadframe interconnect package is tape automated bond (TAB) bonded to circuitry on the chip and which provides a circuit connection for subsequent connection to a printed circuit board as discussed by the authors.
141
Patent
Process for interconnecting conductive substrates using an interposer having conductive plastic filled vias
Nicholas F. Pasch
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TL;DR: In this article, a process for interconnecting conductive substrates using an interposer having conductive plastic filled vias is described, which comprises the steps of forcing conductive material through an end of the through holes in the interPOSer so that raised globs of the conductive polysilicon extend from an opposite end.
134