Patent
Error-correcting encoder, error-correcting decoder and data transmitting system with error-correcting codes
Yasuyuki Sakai,Hideo Yoshida,Toshio Tokita +2 more
- 07 Feb 1995
43
TL;DR: In this paper, an error-correcting encoder and a decoder with a reduced number of shifts was proposed to encode/decode a plurality of information symbols in parallel, which enables a reduction in processing time.
read more
Abstract: The present invention provides an error-correcting encoder and an error-correcting decoder which encode/decode a plurality of information symbols in parallel with a reduced number of shifts, which enables a reduction in the processing time. The error-correcting encoder of the invention includes a shift-register including stages equal to a predetermined number of check symbols for inputting different information symbols in parallel from a plurality of input terminals. The encoder also includes a Galois field multiplier for multiplying each coefficient and a Galois field adder to obtain the predetermined number of check symbols from the information symbols. The encoder can generate the predetermined number of check symbols with shifts, the number of which is reduced according to the number of parallel inputs. The syndrome generator of the error-correcting decoder of the invention includes a plurality of Galois field multipliers which multiply the coefficients for calculating syndromes for inputting different code symbols in parallel from a plurality of input terminals. The syndrome generator also includes a Galois field adder and a shift-register(s) to obtain the predetermined syndrome generating polynomial. The syndrome generator can obtain the desired syndromes with shifts, the number of which is reduced according to the number of parallel inputs.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
Patent
Semiconductor memory device.
Tomoharu Tanaka,Hiroshi Nakamura,Toru Tanzawa +2 more
- 12 Mar 2008
TL;DR: In this paper, the read circuit senses a change in a voltage of the bitline of a bitline, and applies a voltage which is different from the first voltage to the gate of the first transistor when it senses a voltage change.
119
Patent
Product code based forward error correction system
Satish Sridharan,Michael Jarchi,Timothy Coe +2 more
- 04 Jun 2001
TL;DR: In this article, a multidimensional forward error correction system was proposed, which consists of a parallel column decoder and multiple row encoders encoding a (255, 239) BCH code.
96
Patent
Parallel Chien search circuit
Honda Yang,John T. Gill +1 more
- 27 Aug 1998
TL;DR: In this paper, a Chien search circuit for determining roots to an error locator polynomial that is defined by a set of coefficients is presented, where each sub-Chien circuit includes storage elements, storage multipliers, an adder, and a comparator.
93
Patent
Accelerated Reed-Solomon error correction
Jian Gong
- 23 Nov 2000
TL;DR: In this article, a Reed-Solomon decoder is presented that simultaneously searches for m roots of the error locator polynomial and the error magnitude polynomials.
55
Patent
Reed-solomon encoder and decoder
Satish Sridharan,Michael Jarchi +1 more
- 02 Jun 2000
TL;DR: In this paper, a semi-parallel forward error correction system is described, where information symbols comprised of bytes are provided eight bytes in parallel to an encoder which in parallel forms eight bytes of a nonsystematic code word.
49
References
Patent
Method and apparatus for generating Reed-Soloman error correcting code across multiple word boundaries
Daniel P. Leak,John R. Kloeppner +1 more
- 25 Mar 1992
TL;DR: In this paper, an error correction code (ECCECC) generator/checker for processing high bandwidth data block transfers is presented. But the output of the final stage is fed back to the second input of the first stage, and so on.
70
Patent
High bandwidth reed-solomon encoding, decoding and error correcting circuit
Michael C. Riggle,Lih-Jyh Weng,Pak Ning Hui +2 more
- 23 Aug 1988
TL;DR: A pipelined error correction circuit iteratively determines syndromes, error locator and evaluator equations, and error locations and associated error values for received Reed-Solomon code words.
70
Patent
Method and a system for multiple error detection and correction
Grigory Tenengolts
- 16 Mar 1987
TL;DR: In this paper, a method and a system for error detection and correction in which codewords are made up of data and two groups of check symbols is presented. But it is not shown how to detect errors.
63
Patent
Error correction processor and an error correcting method
Yukimi Nakaguchi
- 07 Jun 1995
TL;DR: In this paper, an error correction processing in which operation circuits are provided so as to obtain solutions to the terms of an error position polynomial that is processed from data of coded words read out from a recording medium of which elements comprising Galois fields is presented.
39