Open AccessJournal Article
Encoder and Decoder Design for Convolutional Code based on FPGA
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TL;DR: Simulation results prove the correctness of the designed modules, and these modules can meet the requirements of speed and accuraccy, and BER of the maximum free distance nonmalignant convolutional code in AWGN channel is analyzed.
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Abstract: Firstly,the theory of(2,1,2) convolutional code and the process of Viterbi decoding are described.In addition,FPGA(Field Programmable Gate Array) is employed to implement encoder and Viterbi decoder.Simulation results prove the correctness of the designed modules,and these modules can meet the requirements of speed and accuraccy.Then BER(Bit Error Rate) of the maximum free distance nonmalignant convolutional code in AWGN channel is analyzed.Simulation with Matlab indicates that the convolutional code is powerful in correcting errors,and BER is increasingly reduced when the constraint length of the convolutional code become large,that the convolutional decoder is small in designed output delay,occupies fewer resources,and is of certain practical value.
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Citations
The Design of High Speed and Parallel Convolutional Encoder Based on FPGA
TL;DR: The experimental results show that the convolutional encoding module is capable of handling the input data stream of up to 160Mbps, processing speed, to meet the parallel and real-time of convolutionalist encoding for the channel source of large capacity image data.
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References
The Design of High Speed and Parallel Convolutional Encoder Based on FPGA
TL;DR: The experimental results show that the convolutional encoding module is capable of handling the input data stream of up to 160Mbps, processing speed, to meet the parallel and real-time of convolutionalist encoding for the channel source of large capacity image data.
4