Patent
Element placement method
Angela Digiacomo,Kantilal H. Khokhani +1 more
- 06 Nov 1984
130
TL;DR: In this article, a method for placing a plurality of different size electronic elements having predetermined interconnection requirements there among, on a next level electronic package having an array of element placement positions thereon determines optimum placement in a three pass process.
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Abstract: A method for placing a plurality of different size electronic elements having predetermined interconnection requirements thereamong, on a next level electronic package having an array of element placement positions thereon determines optimum placement in a three pass process. In the first pass, all of the elements are treated as if they are the same size, defined as a unit size, and are assigned to element positions on a unit size next level package, then their placement is optimized. These unit size elements are then replaced by macro size elements, which are approximately the actual size of the corresponding electronic elements. The macro size elements are then rearranged for optimal placement on a macro model image, taking their sizes and shapes into account. Finally, the macro size elements are replaced by actual size elements which are placed on an actual size next level package in element positions, and their placement is again optimized. By optimizing element placement in a three pass process, i.e., unit, macro and actual size, a more efficient placement process is obtained because the element placement program need not take all of the dimensional characteristics of the elements into account at once.
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Citations
Patent
Method and apparatus for designing integrated circuits
V. Corbin Ii Ludlow,Steven G. Danielson,Richard E. Oettel,Mark E. Rossman,James E. Thiele +4 more
- 29 Jun 1989
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David W. Bennett,Eric F. Dellinger,Walter A. Manaker,Carl M. Stern,William R. Troxel,Jay Thomas Young +5 more
- 06 Feb 1995
TL;DR: In this article, a device independent, frequency driven layout system and method for field programmable gate arrays (FPGA) is presented, which allows a circuit designer to specify the desired operating frequencies of clock signals in a given design to the automatic layout system to generate, if possible, a physical FPGA layout which will allow the targeted FPGAs device to operate at the specified frequencies.
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TL;DR: In this article, the authors present a computer system, method and software product that enables automatic placement and routing of datapath functions using a design methodology that preserves hierarchical and structural regularity in top-down designs for datapaths.
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Ranko Scepanovic,James S. Koford,Alexander E. Andreev +2 more
- 28 Jun 1996
TL;DR: In this article, a method for refining the position of linearly aligned cells on the surface of a semiconductor chip is presented, which consists of defining an array of spaces between cells based on maximum and minimum cell positions, establishing a minimum spacing between cells, and linearly shifting cells in a predetermined manner such that no cells are closer to one another than the minimum space between cells.
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