Patent
Efficient thread group scheduling
Ray Joydeep,Appu Abhishek R,Koker Altug,Sinha Kamal,Balaji Vembu,Rajkishore Barik,Eriko Nurvitadhi,Galoppo Von Borries Nicolas C,Tsung-Han Lin,Sanjeev Jahagirdar,Ranganathan Vasanth +10 more
- 11 Oct 2018
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TL;DR: In this paper, a mechanism for intelligent thread scheduling at autonomous machines is described, which is based on detecting dependency information relating to a plurality of threads corresponding to a majority of workloads associated with tasks related to a processor including a graphics processor.
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Abstract: A mechanism is described for facilitating intelligent thread scheduling at autonomous machines. A method of embodiments, as described herein, includes detecting dependency information relating to a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a processor including a graphics processor. The method may further include generating a tree of thread groups based on the dependency information, where each thread group includes multiple threads, and scheduling one or more of the thread groups associated a similar dependency to avoid dependency conflicts.
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Citations
Patent
Scheduler for amp architecture using a closed loop performance and thermal controller
Jeremy C. Andrus,John G. Dorsey,James M. Magee,Daniel A. Chimene,Cyril de la Cropte de Chanterac,Bryan R. Hinch,Aditya Venkataraman,Andrei Dorofeev,Nigel R. Gamble,Russell A. Blaine,Constantin Pistol,James S. Ismail +11 more
- 12 Jan 2018
TL;DR: In this article, a closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state.
3
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Scheduler for AMP architecture with closed loop performance controller using static and dynamic thread grouping
Jeremy C. Andrus,John G. Dorsey,James M. Magee,Daniel A. Chimene,Cyril de la Cropte de Chanterac,Bryan R. Hinch,Aditya Venkataraman,Andrei Dorofeev,Nigel R. Gamble,Russell A. Blaine,Constantin Pistol +10 more
- 12 Jan 2018
TL;DR: In this article, a closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state.
2
Patent
Graphics systems and methods for accelerating synchronization using fine grain dependency check and scheduling optimizations based on available shared memory space
Subramaniam Maiyuran,Varghese George,Koker Altug,Anantaraman Aravindh,Kim Sungye,Valentin Andrei,Ray Joydeep +6 more
- 17 Sep 2020
TL;DR: In this article, a fine-grained dependency check of availability of dependent data or operands in shared local memory or cache when at least one execution unit is available is presented.
1
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Task processing method, device and system, equipment and storage medium
Ding Shengge
- 30 Aug 2019
TL;DR: In this paper, the authors present a task processing method, which comprises the steps of obtaining all tasks corresponding to a target data processing process, generating at least one scheduling unit according to the dependency relationship of each task and the first definition rule, and allocating the task flow as a task group matched with the target processing process to a hardware scheduling component.
1
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Microcontroller-based flexible thread scheduling launching in computing environments
Veernapu Kiran C,Pillai Kamlesh,Valerio James A,Ray Joydeep,Appu Abhishek R +4 more
- 04 Jul 2019
TL;DR: In this paper, a mechanism is described to facilitate microcontroller-based flexible thread scheduling launching in computing environments, which facilitates a graphics processor hosting a microcontroller having a thread scheduling unit, and detection and observation logic to detect a scheduling algorithm associated with an application at the apparatus.
1
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Patent
Instruction level execution preemption
Lacky V. Shah,Gregory Scott Palmer,Gernot Schaufler,Samuel H. Duncan,Philip Browning Johnson,Shirish Gadre,Robert Ohannessian,Nicholas Wang,Christopher Lamb,Philip Alexander Cuadra,Timothy John Purcell +10 more
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8
Patent
Facilitating dynamic runtime transformation of graphics processing commands for improved graphics performance at computing devices
Valerio James A,Abhishek Venkatesh,Satyajit Sarangi,Michael Apodaca,Thomas F. Raoux,Hashem Hashemi,Rama S.B. Harihara +6 more
- 12 Jun 2015
TL;DR: In this article, a mechanism for dynamic runtime transformation of graphics processing commands for improved graphics performance on computing devices is described, which is based on detecting a command stream associated with an application, where the command stream includes dispatches.
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