Efficient Test Compaction for Pseudo-Random Testing
Sheng Zhang,Sharad C. Seth,Bhargab B. Bhattacharya +2 more
- 18 Dec 2005
- pp 337-342
TL;DR: Experimental results show that the proposed test-cube finding algorithm outperforms comparable schemes reported in the literature and covers the test vectors by test cubes that are one to two orders of magnitude smaller in number with a much smaller increase in the percentage of specified bits.
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Abstract: Compact set of 3-valued test vectors for random pattern resistant faults are covered in multiple test passes. During a pass, its associated test cube specifies certain bits in the scan chain to be held fixed and others to change pseudo -randomly. We propose an algorithm to find a small number of cubes to cover all the test vectors, thus minimizing total test length. The test-cube finding algorithm repeatedly evaluates small perturbations of the current solution so as to maximize the expected test coverage of the cube. Experimental results show that our algorithm covers the test vectors by test cubes that are one to two orders of magnitude smaller in number with a much smaller increase in the percentage of specified bits. It outperforms comparable schemes reported in the literature
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Citations
Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression
Dariusz Czysz,Grzegorz Mrugalski,Nilanjan Mukherjee,Janusz Rajski,P. Szczerbicki,Jerzy Tyszer +5 more
TL;DR: It is demonstrated that compression ratios can be order of magnitude higher, if the cube merging continues despite conflicts on certain positions, and that test clusters make it possible to deliver test patterns in a flexible power-aware fashion.
50
Patent
Test generation methods for reducing power dissipation and supply currents
Xijiang Lin,Janusz Rajski +1 more
- 09 Feb 2010
TL;DR: In this paper, a test cube is generated targeting one or more faults in the circuit design and then modified by specifying at least a portion of the unspecified values with values determined at least in part from the hold probabilities and stored.
24
Accumulator Based 3-Weight Pattern Generation
TL;DR: An accumulator-based 3-weight test pattern generation scheme is presented, which can be efficiently utilized to drive down the hardware of BIST pattern generation, as well as compare favorably with respect to the required hardware.
23
An efficient test-data compaction for low power VLSI testing
Po-Han Wu,Tsung-Tang Chen,Wei-Lin Li,Jiann-Chyi Rau +3 more
- 18 May 2008
TL;DR: This paper presents an input test data compaction and scan power reduction technique and presents new design for testability (DFT) method to hold values when some of test data in test cubes are not need to be changed.
12
Efficient Weighted Pattern Generation Technique With Low Hardware Overhead
K. Veena Madhavi,M. Nirmala,M. Tech Student +2 more
- 01 Jan 2013
TL;DR: An accumulator-based 3-weight test pattern generation scheme is presented, which can be efficiently utilized to drive down the hardware of BIST pattern generation, as well as compare favorably with respect to the required hardware.
2
References
•Book
Computers and Intractability: A Guide to the Theory of NP-Completeness
Michael Randolph Garey,David S. Johnson +1 more
- 01 Jan 1979
TL;DR: The second edition of a quarterly column as discussed by the authors provides a continuing update to the list of problems (NP-complete and harder) presented by M. R. Garey and myself in our book "Computers and Intractability: A Guide to the Theory of NP-Completeness,” W. H. Freeman & Co., San Francisco, 1979.
Compactest: a method to generate compact test sets for combinational circuits
Irith Pomeranz,L.N. Reddy,Sudhakar M. Reddy +2 more
- 26 Oct 1991
TL;DR: Heuristics to aid the derivation of small test sets that detect single stuck-at faults in combinational logic circuits are proposed and can be added to existing test pattern generators without compromising fault coverage.
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