Efficient sparse matrix multiple-vector multiplication using a bitmapped format

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1. What have the authors contributed in "Efficient sparse matrix multiple-vector multiplication using a bitmapped format" ?

2. What future works have the authors mentioned in the paper "Efficient sparse matrix multiple-vector multiplication using a bitmapped format" ?

3. What are the reasons for the low utilisation of sparse matrix multiplication routines?

4. What is the aim of this work?

Accepted Answer

Kannan et al. this paper proposed a block-based sparse matrix multiplication algorithm for the MBR format.

Accepted Answer

There is ample scope to tune performance by modifying parameters such as the block size and effects of such tuning will be the topic of future work.. This article has focussed on establishing the performance of the MBR format and the algorithm for sequential execution, paving the way for its parallelization, which will be explored in future work.

Accepted Answer

The reasons for the low utilisation are a) indexing overheads associated with storing and accessing elements of sparse matrices and b) irregular memory accesses leading to low reuse of entries loaded in caches and registers.

Accepted Answer

whilst bitmasked CSB is geared towards optimizing parallel execution, the aim of this work is to obtain a high throughput for multiple vectors in the sequential case.

Accepted Answer

The sparse matrix × vector (SpMV) and sparse matrix ×multiple-vector (SMMV) multiplication routines are key kernels in many sparse matrix computations used in numerical linear algebra, including iterative linear solvers and sparse eigenvalue solvers.

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The implication of this trend is that there is an increasing need for devising algorithms, methods and storage formats that obtain higher processor utilization by reducing communication.

Accepted Answer

MKL is faster than MBR on four matrices: dielfilterV2real, dielfilterv3real, ASIC 680k and nlpkkt80, which come from different applications.

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Both the Opteron and Xeon support the 128- bit SSE4 instruction set that allows operating on 2 double floating point number in a single instruction.

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The CSR format stores the nonzero entries in an array val of the relevant datatype (single precision, double precision or integers).

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The Compressed Sparse Row (CSR) format [Barrett et al. 1994] (or its variant, the Compressed Sparse Column format) can be regarded as the de-facto standard format for storing and manipulating sparse matrices.

Accepted Answer

The cost of index-calculation and looping can be amortized by increasing the amount of workAlgorithm 5 Looping over set bits for a bitmap x of length 8 bits.

Accepted Answer

For an n × n sparse matrix with z nonzeros (z > n) and at least one nonzero per row and per column, the minimum number b of r × r blocks required to pack the entries is z/r2 and the maximum is min(z, n2/r2).

Accepted Answer

Algorithm 4 A modification to steps 4–8 Algorithm 3.1 ... 2 for each set bit p in map 3 i: = p%r + bi× r, j: = p%c+ bj × c 4 y(i)+ = *val× x(j) 5 increment valThe key detail is iterating over set bits in ‘for each’.

Accepted Answer

There is ample scope to tune performance by modifying parameters such as the block size and effects of such tuning will be the topic of future work.

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The Intel Harpertown-based Xeon E5450 on the other hand has access to 12 MB of L2 cache, shared between 4 cores on a single processor, each operating at 3 GHz.

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Since the MKL library is closed-source software, it is not possible to determine why mkl dcsrmm is not optimized to take advantage of multiple vectors.

Accepted Answer

The format partitions the matrix into “compressed sparse” blocks of bit-mapped register blocks, resulting in two levels of blocking.

Accepted Answer

To determine the positions of trailing bits, the authors first isolate the trailing bit and then use de Bruijn sequences to find its position in the word, based on a technique proposed by Leiserson et al in [Leiserson et al. 1998].

Efficient sparse matrix multiple-vector multiplication using a bitmapped format

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Most frequently asked questions

1. What have the authors contributed in "Efficient sparse matrix multiple-vector multiplication using a bitmapped format" ?

2. What future works have the authors mentioned in the paper "Efficient sparse matrix multiple-vector multiplication using a bitmapped format" ?

3. What are the reasons for the low utilisation of sparse matrix multiplication routines?

4. What is the aim of this work?

5. What are the key kernels in sparse matrix computations?

6. What is the implication of this trend?

7. What are the four matrices that are faster than MBR?

8. What instruction set does the Opteron and Xeon support?

9. What is the format for storing nonzero entries in an array?

10. What is the format for storing and manipulating sparse matrices?

11. How much work can be done to calculate a bitmap?

12. What is the minimum number of blocks required to pack the entries?

13. What is the key detail of the algorithm?

14. What is the scope of tuning performance?

15. How many MB of cache does the Xeon E5450 have?

16. Why is mkl dcsrmm not optimized to take advantage of multiple?

17. What is the format for storing blocks of bit-mapped register blocks?

18. What is the simplest way to determine the positions of trailing bits?

Figures

Citations

Shifted Cholesky QR for Computing the QR Factorization of Ill-Conditioned Matrices

Shifted CholeskyQR for computing the QR factorization of ill-conditioned matrices

Accelerating Framework of Transformer by Hardware Design and Model Compression Co-Optimization.

Regularizing irregularity: bitmap-based and portable sparse matrix multiplication for graph data on GPUs

A fast implementation of MLR-MCL algorithm on multi-core processors

References

The university of Florida sparse matrix collection

Templates for the Solution of Linear Systems: Building Blocks for Iterative Methods

Hitting the memory wall: implications of the obvious

Ascertaining Uncertainty for Efficient Exact Cache Analysis

Reflections on the memory wall

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