Proceedings Article10.1109/TEST.2004.1386936
Efficient pattern mapping for deterministic logic BIST
V. Gherman,Hans-Joachim Wunderlich,Harald Vranken,Friedrich Hapke,M. Wittke,M. Garbers +5 more
- 26 Oct 2004
- pp 48-56
TL;DR: A novel DLBIST synthesis procedure that has nearly linear complexity in terms of both computing time and memory consumption is proposed and the efficiency of the new algorithms for industrial designs up to 2M gates is demonstrated.
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Abstract: Deterministic logic BIST (DLBIST) is an attractive test strategy, since it combines advantages of deterministic external testing and pseudo-random LBIST. Unfortunately, previously published DLBIST methods are unsuited for large ICs, since computing time and memory consumption of the DLBIST synthesis algorithms increase exponentially, or at least cubically, with the circuit size. In this paper, we propose a novel DLBIST synthesis procedure that has nearly linear complexity in terms of both computing time and memory consumption. The new algorithms are based on binary decision diagrams (BDDs). We demonstrate the efficiency of the new algorithms for industrial designs up to 2M gates.
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Citations
X-masking during logic BIST and its impact on defect coverage
Yuyi Tang,Hans-Joachim Wunderlich,P. Engelke,Ilia Polian,Bernd Becker,J. Schloffel,Friedrich Hapke,M. Wittke +7 more
- 26 Oct 2004
TL;DR: An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.
Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression
Dariusz Czysz,Grzegorz Mrugalski,Nilanjan Mukherjee,Janusz Rajski,P. Szczerbicki,Jerzy Tyszer +5 more
TL;DR: It is demonstrated that compression ratios can be order of magnitude higher, if the cube merging continues despite conflicts on certain positions, and that test clusters make it possible to deliver test patterns in a flexible power-aware fashion.
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Restrict Encoding for Mixed-Mode BIST
Abdul-Wahid Hakmi,Stefan Holst,Hans-Joachim Wunderlich,J. Schloffel,Friedrich Hapke,A. Glowatz +5 more
- 03 May 2009
TL;DR: This paper presents a synthesis technique for a mixed-mode BIST scheme which is able to exploit the regularities of a deterministic test pattern set for minimizing the hardware overhead and memory requirements.
Operating system scheduling for efficient online self-test in robust systems
Yanjing Li,Onur Mutlu,Subhasish Mitra +2 more
- 02 Nov 2009
TL;DR: The need for operating system (OS) support to efficiently orchestrate online self-test in future robust systems is demonstrated, with techniques that eliminate any performance degradation and perceptible delays in soft real-time and interactive applications and significantly reduce the impact of onlineself-test on the performance of computation-intensive applications.
Low-Power Programmable PRPG With Test Compression Capabilities
Michal Filipek,Grzegorz Mrugalski,Nilanjan Mukherjee,Benoit Nadeau-Dostie,Janusz Rajski,Jedrzej Solecki,Jerzy Tyszer +6 more
TL;DR: An LP test compression method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the PRESTO-based logic BIST (LBIST) infrastructure is proposed.
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References
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Janusz Rajski,Jerzy Tyszer,M. Kassab,Nilanjan Mukherjee,Rob Thompson,Kun-Han Tsai,A. Hertwig,Nagesh Tamarapalli,Grzegorz Mrugalski,Geir Eide,Jun Qian +10 more
- 07 Oct 2002
TL;DR: Embedded deterministic test technology is introduced, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time.
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