Proceedings Article10.1109/VTEST.1998.670867
Efficient path selection for delay testing based on partial path evaluation
Seiichiro Tani,Mitsuo Teramoto,Tomoo Fukazawa,Kazuyoshi Matsuhiro +3 more
- 26 Apr 1998
- pp 188-193
41
TL;DR: Experimental results show the proposed efficient path selection method for path delay testing can select about one percent of the paths selected by a conventional method without decreasing fault coverage.
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Abstract: In this paper, we propose an efficient path selection method for path delay testing. The proposed method selects a very small set of paths for delay testing that covers all paths. Path selection is done by judging which of two paths has the larger real delay by taking into account the ambiguity of calculated delay, caused by imprecise delay modeling as well as process disturbance. In order to make precise judgement under this ambiguity, the delays of only unshared segments between the two paths are evaluated. This is because the shared segments are presumed to have the same real delays on both paths. Experimental results show the method can select about one percent of the paths selected by a conventional method without decreasing fault coverage.
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Citations
Critical path selection for delay fault testing based upon a statistical timing model
TL;DR: This paper provides theoretical analysis to demonstrate that the new path-selection problem consists of two computationally intractable subproblems, and discusses practical heuristics and their performance with respect to each subproblem.
97
Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices
TL;DR: The experimental results demonstrate the difference in estimated circuit performance for the case when power supply noise effects are considered versus when these effects are ignored and indicate the need for considering power supply Noise effects on delays during path selection and dynamic timing analysis.
74
Testing for Transistor Aging
Altug Hakan Baba,Subhasish Mitra +1 more
- 03 May 2009
TL;DR: On-line circuit failure prediction, together with on-line self-test, can overcome transistor aging challenges for robust systems with built-in self-healing for future systems.
68
Longest-path selection for delay test under process variation
TL;DR: An efficient method to generate the set of longest paths for delay test under process variation is presented and a novel technique is proposed to prune paths that are not longest, resulting in a significant reduction in the number of paths.
60
Path selection for delay testing of deep sub-micron devices using statistical performance sensitivity analysis
Jing-Jia Liou,Kwang-Ting Cheng,D.A. Mukherjee +2 more
- 30 Apr 2000
TL;DR: A novel path and segment selection methodology for delay testing based on the results of statistical performance sensitivity analysis is proposed, which defines a new path/segment searching paradigm for detecting delay faults in deep sub-micron devices.
50
References
•Book
Digital Systems Testing and Testable Design
Miron Abramovici,M.A. Breuer,Arthur D. Friedman +2 more
- 01 Jan 1990
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
2.9K
On path selection in combinational logic circuits
TL;DR: Algorithms to select such sets of paths with minimum cardinality that includes at least one path, with maximum modeled delay, for each circuit lead or gate input are given.
191
Delay testing for non-robust untestable circuits
Kwang-Ting Cheng,H.-C. Chen +1 more
- 17 Oct 1993
TL;DR: This paper takes a closer look at the properties of these non-robust untestable faults with the goal of determining whether and how these faults should be tested.
161
Fast Identification of Robust Dependent Path Delay Faults
U. Sparmann,D. Luxenburger,Kwang-Ting Cheng,Sudhakar M. Reddy +3 more
- 01 Jan 1995
TL;DR: A theory is developed which puts the work of these papers into a common framework, thus allowing for a better understanding of their relation, and a new algorithm which trades quality of the result against computation time, and allows handling of large circuits with tens of millions of paths.
87
Delay Fault Coverage and Performance Tradeoffs
William K. C. Lam,Alexander Saldanha,Robert K. Brayton,Alberto Sangiovanni-Vincentelli +3 more
- 01 Jul 1993
TL;DR: It is shown that 100% delay fault testability is not necessary to guarantee the speed of a combinational circuit because there exist path delay faults which can never impact the circuit delay unless some other pathdelay faults also affect it.
83
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