Open AccessProceedings Article
Efficient parallel algorithms for processor arrays.
Kuang-Hua Huang,Jacob A. Abraham +1 more
- 01 Jan 1982
- pp 268-279
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TL;DR: A measure is proposed which can calculate the efficiency of an algorithm performed in a processor array, and this measure is used to compare several proposed array architectures for a variety of algorithms.
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Abstract: With the advent of VLSI technology, it is possible to provide extremely high but inexpensive computational capability with a system consisting of a large number of identical processors organised in a simple, regular structure. In order to exploit the high computational capability of the arrays, however, it is important to employ an efficient parallel algorithm. In this paper a measure is proposed which can calculate the efficiency of an algorithm performed in a processor array. This measure is used to compare several proposed array architectures for a variety of algorithms. Finally, efficient parallel algorithms for recursive filtering problems, matrix-vector multiplication, and matrix multiplication are also proposed. 7 references.
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Citations
Algorithm-Based Fault Tolerance for Matrix Operations
Kuang-Hua Huang,Abraham +1 more
TL;DR: Algorithm-based fault tolerance schemes are proposed to detect and correct errors when matrix operations such as addition, multiplication, scalar product, LU-decomposition, and transposition are performed using multiple processor systems.
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The design of concurrent error diagnosable systolic arrays for band matrix multiplications
S.-W. Chan,Chin-Long Wey +1 more
TL;DR: Recent efforts to optimize the performance of a band matrix multiplication systolic array (BMMSA) is discussed, concentrating on the fundamental differences between the Kung-Leiserson and Huang-Abraham schemes of syStolic design in order to exemplify the extremes in design philosophies.
38
Systolic arrays for finite element analysis
TL;DR: Systolic assembly-factorization networks for the stiffness method and the natural factor approach of finite element analysis are presented to chain together two or more systolic arrays with compatible data flow patterns such that regularity of data flow can be maintained.
15
High-performance systolic arrays for band matrix multiplication
Yun Yang,Wenqing Zhao,Yasuaki Inoue +2 more
- 23 May 2005
TL;DR: Three high-performance band matrix multiplication systolic arrays (BMMSA) are presented, based on the ideas of "matrix compression" and "super pipelining", which show that the best syStolic array for band matrix multiplying uses almost 100% of the processing elements (PE) in each step.
12
VLSI systems for band matrix multiplication
Kam-Hoi Cheng,Sartaj Sahni +1 more
- 01 Jun 1987
TL;DR: This paper examines several VLSI architectures and compares these for their suitability for various forms of the band matrix multiplication problem, and provides correctness proofs for selected designs to illustrate how VLSi designs may be proved correct using traditional mathematical tools.
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