Efficient Embedding of Deterministic Test Data
Mudassar Majeed,Daniel Ahlstrom,Urban Ingelsson,Gunnar Carlsson,Erik Larsson +4 more
- 01 Dec 2010
- pp 159-162
TL;DR: This paper presents an approach to efficiently embed deterministic test patterns in the system by taking structural information of the system into account, and stores only commands and component-specific test sets per each unique component.
read more
Abstract: Systems with many integrated circuits (ICs), often of the same type, are increasingly common to meet the constant performance demand. However, systems in recent semiconductor technologies require not only manufacturing test, but also in-field test. Preferably, the same test set is utilized both at manufacturing test and in-field test. While deterministic test patterns provide high fault coverage, storing complete test vectors leads to huge memory requirements and inflexibility in applying tests. In an IEEE 1149.1 (Boundary scan) environment, this paper presents an approach to efficiently embed deterministic test patterns in the system by taking structural information of the system into account. Instead of storing complete test vectors, the approach stores only commands and component-specific test sets per each unique component. Given a command, test vectors are created by a test controller during test application. The approach is validated on hardware and experiments on ITC’02 benchmarks and industrial circuits show that the memory requirement for storing the test data for a system is highly related to the number of unique components.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Figures
Citations
Fault injection and fault handling: An MPSoC demonstrator using IEEE P1687
Kim Petersen,Dimitar Nikolov,Urban Ingelsson,Gunnar Carlsson,Farrokh Ghani Zadegan,Erik Larsson +5 more
- 07 Jul 2014
TL;DR: An MPSoC demonstrator that enables experimentation on fault injection and fault handling and uses the existing test features, i.e. IEEE P1687 infrastructure, to assist fault handling is developed.
13
Fault management in an IEEE P1687 (IJTAG) environment
Erik Larsson,Konstantin Sibin +1 more
- 18 Apr 2012
TL;DR: To meet the constant demand for performance, it is increasingly common with multi-processor system-on-chips (MPSoCs) to create integrated circuits (ICs) that contain billions of transistors squeezed on a few square centimeters.
Fault injection and fault handling: an MPSoC demonstrator using IEEE P1687
Kim Petersen,Dimitar Nikolov,Urban Ingelsson,Gunnar Carlsson,Farrokh Ghani Zadegan,Erik Larsson +5 more
- 01 Jan 2014
TL;DR: In this article, an MPSoC model with a set of components (devices) each equipped with fault detection features, so called instruments, an Instrument Access Infrastructure (IAI) based on IEEE P1687 that connects the instruments, a Fault Indication and Propagation Infrastructure (FIPI) that propagates fault indications to system-level, a Resource Manager (RM) to schedule jobs based on fault statuses, and a Fault Injection Manager (FIM) that inserts faults.
12
Area-efficient high-coverage LBIST
Nan Li,Elena Dubrova +1 more
TL;DR: This paper presents a new method for on-chip generation of deterministic test patterns based on registers with non-linear update that can achieve a higher stuck-at coverage than the test point insertion with less area overhead.
10
Patent
Test access system, method and computer-accessible medium for chips with spare identical cores
Ozgur Sinanoglu
- 07 Jun 2013
TL;DR: In this paper, a multi-core chip can fail the test if the number of defective cores can be greater than the number number of spare cores plus 1 using a comparator.
7
References
Logic BIST for large industrial designs: real issues and case studies
Graham G. Hetherington,T. Fryars,Nagesh Tamarapalli,M. Kassab,A. Hassan,Janusz Rajski +5 more
- 28 Sep 1999
TL;DR: The experimental results demonstrate that with automation of the proposed solutions, logic BIST can achieve test quality approaching that of ATPG with minimal area overhead and few changes to the design flow.
329
A set of benchmarks for modular testing of SOCs
Erik Jan Marinissen,Vijay S. Iyengar,Krishnendu Chakrabarty +2 more
- 07 Oct 2002
TL;DR: The paper defines the benchmark format and naming scheme, and presents the benchmark SOCs, and provides an overview of the research problems that can be addressed and evaluated by means of this benchmark set.
321
CASP: concurrent autonomous chip self-test using stored test patterns
Yanjing Li,Samy Makar,Subhasish Mitra +2 more
- 10 Mar 2008
TL;DR: CASP enables design of robust systems with built-in features for circuit failure prediction, error detection, self-diagnosis and self-repair to overcome major reliability challenges in scaled-CMOS technologies.
Test data compression for IP embedded cores using selective encoding of scan slices
Zhanglei Wang,Krishnendu Chakrabarty +1 more
- 08 Nov 2005
TL;DR: A selective encoding method that reduces test data volume and test application time for scan testing of intellectual property (IP) cores and derives an upper bound on the density of care bits that allows it to achieve the best-case compression.
A geometric-primitives-based compression scheme for testing systems-on-a-chip
Aiman H. El-Maleh,S. al Zahir,Esam Khan +2 more
- 29 Mar 2001
TL;DR: A novel and very efficient lossless compression technique for testing systems-on-a-chip based on geometric shapes that exploits reordering of test vectors to minimize the number of shapes needed to encode the test data.