Proceedings Article10.1109/APCCAS.2008.4746351
Efficient decoder design for high-throughput LDPC decoding
Zhiqiang Cui,Zhongfeng Wang,Xinmiao Zhang,Qingwei Jia +3 more
- 01 Nov 2008
- pp 1640-1643
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TL;DR: A matrix permutation scheme is proposed to convert a generic QC-LDPC code to a shift-structured LDPC code, and novel implementation schemes for min-sum algorithm based column-layered decoding are presented.
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Abstract: In this paper, a matrix permutation scheme is proposed to convert a generic QC-LDPC code to a shift-structured LDPC code. Thus, efficient VLSI architectures can be developed to achieve very high decoding throughput with low hardware complexity. Furthermore, novel implementation schemes for min-sum algorithm based column-layered decoding are presented. The proposed approaches provide very efficient ways for high-speed decoder design of generic QC-LDPC codes.
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Citations
Patent
Decoder and decoding method for low-density parity check codes constructed based on reed-solomon codes
Yeong-Luh Ueng,Kuan-Chieh Wang,Chun-Jung Chen,Tsung Chieh Yang +3 more
- 12 Nov 2010
TL;DR: In this paper, the variable nodes are partitioned into several groups, and each group is processed sequentially in order to shorten the critical-path delay and, hence, increase the maximum operating frequency.
28
Efficient graphics processing unit based layered decoders for quasicyclic low-density parity-check codes
TL;DR: The experimental results show that the proposed layered LDPC decoder has good bit error ratio (BER) performance comparable to TPMP decoder and can achieve a performance improvement of 2.3 times compared to the existing fastest GPU‐based implementation.
14
Efficient layer stopping technique for layered LDPC decoding
TL;DR: A layer stopping criterion is proposed to reduce further the operations within iterative layered LDPC decoding by efficiently reducing the layer operations by up to 60% with a negligible loss of coding gain at Eb /N 0 of 3.2 dB.
12
Efficient EMS decoding for non-binary LDPC codes
Leixin Zhou,Jin Sha,Zhongfeng Wang +2 more
- 01 Nov 2012
TL;DR: A novel approach is proposed for EMS NB-LDPC decoding, compared to EMS decoding algorithm, the message memory and the average number of iterations have been reduced and the overall decoder architecture is proposed.
9
Patent
Column-layered message-passing ldpc decoder
Xinmiao Zhang,Alexander Bazarsky,Ran Zamir,Eran Sharon,Idan Alrod,Omer Fainzilber,Sanel Alterman +6 more
- 23 Aug 2016
TL;DR: In this article, a decoder includes a variable node unit (VNU) that includes variable-to-check lookup table circuit configured to output a variable to check message corresponding to a check node.
8
References
•Book
Low-Density Parity-Check Codes
Robert G. Gallager
- 01 Jan 1963
TL;DR: A simple but nonoptimum decoding scheme operating directly from the channel a posteriori probabilities is described and the probability of error using this decoder on a binary symmetric channel is shown to decrease at least exponentially with a root of the block length.
Near optimum universal belief propagation based decoding of low-density parity check codes
Jinghu Chen,Marc P. C. Fossorier +1 more
TL;DR: A belief-propagation (BP)-based decoding algorithm which utilizes normalization to improve the accuracy of the soft values delivered by a previously proposed simplified BP-based algorithm is proposed.
758
Shuffled iterative decoding
TL;DR: Simulations show that the new schedules of iterative decoding of low-density parity-check codes and turbo codes offer better performance/complexity tradeoffs, especially when the maximum number of iterations has to remain small.
An efficient message-passing schedule for LDPC decoding
Eran Sharon,Simon Litsyn,Jacob Goldberger +2 more
- 30 Nov 2004
TL;DR: An efficient decoding schedule for low-density parity-check (LDPC) codes that outperforms the conventional approach, in terms of both complexity and performance, is presented.
A class of good quasi-cyclic low-density parity check codes based on progressive edge growth graph
Zongwang Li,B.V.K.V. Kumar +1 more
- 07 Nov 2004
TL;DR: Simulations show that a new class of quasi-cyclic low density parity check (QC-LDPC) codes, designed by modifying the progressive edge growth (PEG) graph, offer hardware-friendly parity check matrices and have as good error correction performance as random LDPC codes and other good QC-LD PC codes.
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