Efficient code density through look-up table compression
Talal Bonny,Joerg Henkel +1 more
- 16 Apr 2007
- pp 809-814
TL;DR: This paper introduces a novel and efficient hardware-supported approach that belongs to the group of statistical compression schemes as it is based on canonical Huffman coding, and is the first to also compress the necessary Look-up Tables that can become significant in size if the application is large and/or high compression is desired.
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Abstract: Code density is a major requirement in embedded system design since it not only reduces the need for the scarce resource memory but also implicitly improves further important design parameters like power consumption and performance. Within this paper we introduce a novel and efficient hardware-supported approach that belongs to the group of statistical compression schemes as it is based on Canonical Huffman Coding. In particular, our scheme is the first to also compress the necessary Look-up Tables that can become significant in size if the application is large and/or high compression is desired. Our scheme optimizes the number of generated Look-up Tables to improve the compression ratio. In average, we achieve compression ratios as low as 49% (already including the overhead of the Lookup Tables). Thereby, our scheme is entirely orthogonal to approaches that take particularities of a certain instruction set architecture into account. We have conducted evaluations using a representative set of applications and have applied it to three major embedded processor architectures, namely ARM, MIPS and PowerPC.
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Citations
A Twofold Lookup Table Architecture for Efficient Approximation of Activation Functions
TL;DR: A novel approach to reduce hardware resource consumption when neural networks (NNs) are deployed on field-programmable gate array (FPGA) boards is proposed, based on a twofold LUT (t-LUT) architecture, which comprises an error-Lut (e- LUT) and a data-L UT (d-Lutt) in order to achieve high precision and speed as well as lowHardware resource consumption.
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Efficient Code Compression for Embedded Processors
Talal Bonny,Jorg Henkel +1 more
TL;DR: A novel, hardware-supported approach that optimizes the number and size of generated LUTs to improve the compression ratio and is orthogonal to approaches that take particularities of a certain instruction set architecture into account.
24
Instruction splitting for efficient code compression
Talal Bonny,Jorg Henkel +1 more
- 04 Jun 2007
TL;DR: This paper introduces a novel and efficient hardware-supported approach to code compression that reduces the size of the generated decoding table by splitting instructions into portions of varying size before Huffman coding compression is applied.
21
Huffman-based code compression techniques for embedded processors
Talal Bonny,Jorg Henkel +1 more
TL;DR: This article introduces a novel and efficient hardware-supported compression technique that is based on Huffman Coding, which reduces the size of the generated decoding table, which takes a large portion of the memory.
21
Code density concerns for new architectures
Vincent M. Weaver,Sally A. McKee +1 more
- 04 Oct 2009
TL;DR: A hand-optimization of an assembly language embedded benchmark for size on 21 different instruction set architectures finds that the architectural features that contribute most heavily to code density are instruction length, number of registers, availability of a zero register, bit-width, hardware divide units, and the availability of unaligned loads and stores.
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Charles R. Lefurgy,Peter L. Bird,I-Cheng Chen,Trevor Mudge +3 more
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TL;DR: This work proposes a method for compressing programs in embedded processors where instruction memory size dominates cost and achieves an average size reduction of 39%, 34%, and 26%, respectively, for SPEC CINT95 programs.
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TL;DR: A low-power processor architecture is described dedicatedly for embedded application programs by means of an object code compression approach that unifies duplicated instructions existing in the embedded program and assigns a compressed object code to such an instruction.
Compiler-driven cached code compression schemes for embedded ILP processors
Sergei Y. Larin,Thomas M. Conte +1 more
- 16 Nov 1999
TL;DR: Experiments found that when the missprediction penalty of the added Huffman decoder stage was taken into account, a Tailored ISA approach produced higher performance, while providing higher ROM size savings.
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