Dynamically Reconfigurable Systems
Marco Platzner,Jürgen Teich,Norbert Wehn +2 more
- 01 Jan 2010
46
About: The article was published on 01 Jan 2010.
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Citations
FPGA Dynamic and Partial Reconfiguration: A Survey of Architectures, Methods, and Applications
Kizheppatt Vipin,Suhaib A. Fahmy +1 more
TL;DR: This work reviews FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures, and investigates design flows and identifies the key challenges in making reconfigurable FPGAs systems easier to design.
Adaptive Dynamic On-chip Memory Management for FPGA-based reconfigurable architectures
Ghada Dessouky,Michael J. Klaiber,Donald G. Bailey,Sven Simon +3 more
- 20 Oct 2014
TL;DR: The proposed scalable BRAM memory management architecture adaptively manages these dynamic memory requirements and balances the buffer memory over several PEs to reduce the total memory required, compared to the worst-case memory footprint for all PEs.
29
RRAM-based FPGA for “Normally Off, Instantly On” applications
Ogun Turkyilmaz,Santhosh Onkaraiah,Marina Reyboz,Fabien Clermidy,Hraziia,Costin Anghel,Jean-Michel Portal,Marc Bocquet +7 more
TL;DR: This paper proposes to integrate non-volatile resistive memories in the configuration cells and registers in order to instantly restore the FPGA context and shows that if the circuit is in the ‘ON’ state for less than 42% of time, non-Volatile FPGa starts saving energy compared to classical FPGAs.
28
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration
Dionisios Pnevmatikatos,Kyprianos Papadimitriou,Tobias Becker,Peter Böhm,Andreas Brokalakis,Karel Bruneel,Catalin Bogdan Ciobanu,Tom Davidson,Georgi Gaydadjiev,Karel Heyse,Wayne Luk,Xinyu Niu,Ioannis Papaefstathiou,Danilo Pau,Oliver Pell,Christian Pilato,Marco D. Santambrogio,Donatella Sciuto,Dirk Stroobandt,Tim Todman,Elias Vansteenkiste +20 more
TL;DR: The FASTER project will facilitate the use of reconfigurable technology by providing a complete methodology that enables designers to easily specify, analyse, implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigured technology.
17
Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms
Adrian Lifa
- 31 Aug 2015
TL;DR: This research presents a meta-modelling architecture that automates the very labor-intensive and therefore time-heavy and therefore expensive process of designing and integrating embedded systems to manage and manage distributed systems.
References
Elliptic Curve Arithmetic
Richard Crandall,Carl Pomerance +1 more
- 01 Jan 2001
TL;DR: The history of what are called elliptic curves goes back well more than a century as mentioned in this paper, and they have found their way into abstract and computational number theory, and now sit squarely as a primary tool.
26
No-break dynamic defragmentation of reconfigurable devices
Sándor P. Fekete,Tom Kamphans,Nils Schweer,Christopher Tessars,J.C. van der Veen,Josef Angermeier,Dirk Koch,Jürgen Teich +7 more
- 23 Sep 2008
TL;DR: In this article, the authors propose a new method for defragmenting the module layout of a reconfigurable device, enabled by a novel approach for dealing with communication needs between relocated modules and with inhomogeneities found in commonly used FPGAs.
ReCoNets—Design Methodology for Embedded Systems Consisting of Small Networks of Reconfigurable Nodes and Connections
Christian Haubelt,Dirk Koch,Felix Reimann,Thilo Streichert,Jürgen Teich +4 more
- 01 Jan 2010
TL;DR: This chapter will present the ReCoNets approach for increasing reliability and flexibility of automotive, avionic or body-area networks by solving the hardware/software codesign problem online.
15
Minimizing Communication Cost for Reconfigurable Slot Modules
Sándor P. Fekete,Jan C. van der Veen,Mateusz Majer,Jürgen Teich +3 more
- 01 Aug 2006
TL;DR: This work presents integer linear programming (ILP) formulations that address the problem of communication-aware module placement in array-like reconfigurable environments, such as the Erlangen Slot Machine.
15
Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device
TL;DR: In this article, an online and an offline component for the defragmentation of the available space is proposed, where the sequence of modules to be loaded on the FPGA is unknown beforehand.
13