Dynamic task binding for hardware/software reconfigurable networks
Thilo Streichert,Christian Strengert,Christian Haubelt,Jürgen Teich +3 more
- 28 Aug 2006
- pp 38-43
TL;DR: A hardware/software partitioning algorithm for reconfigurable networks that optimizes the task binding onto resources at runtime such that node/link defects can be handled and data traffic on links between computational nodes will be minimized.
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Abstract: In this paper, a new methodology for tolerating link as well as node defects in self-adaptive reconfigurable networks will be presented. Currently, networked embedded systems need a certain level of redundancy for each node and link in order to tolerate defects and failures in a network. Due to monetary constraints as well as space and power limitations, the replication of each node and link is not an option in most embedded systems. Therefore, we will present a hardware/software partitioning algorithm for reconfigurable networks that optimizes the task binding onto resources at runtime such that node/link defects can be handled and data traffic on links between computational nodes will be minimized. This paper presents a new hardware/software partitioning algorithm, an experimental evaluation and for demonstrating the realizability, an implementation on a network of FPGA-based boards.
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Figures
Figure 6: Distance and its standard deviation between the Pareto-optimal partitions determined by an EA and the online partitioner over time (number of task migrations). 
Figure 7: Normalized traffic T and percentage of suboptimally bound tasks N over time (number of task migrations). 
Figure 1: Functionality is modeled with a so-called sensor-controller-actuator chain. This functionality will be bound with certain restrictions onto the nodes of the network topology. 
Figure 2: Shown are four cases of a network: a) normal operation b) after a node defect c) after reestablishing communication and switching to replicated tasks and d) after an optimization phase 
Figure 4: Shown are two tasks tc1, t c 2 at a computational node c1. The inter task communication is denoted with directed edges to/from the ports or between tc1 and t c 2. Annotated to each edge is the traffic between two tasks. 
Figure 3: During the fast repair phase, the replicated tasks take over the control and the communication between two tasks will be reestablished. The optimization phase optimizes the binding of tasks and creates new replicas.
Citations
A task remapping technique for reliable multi-core embedded systems
Chanhee Lee,Hokeun Kim,Hae-woo Park,Sungchan Kim,Hyunok Oh,Soonhoi Ha +5 more
- 24 Oct 2010
TL;DR: The proposed task remapping technique outperforms the previous works with respect to application throughput and is examined on both space and run-time overhead for compile-time analysis varying the number of failed processors.
83
Approximately-Timed Performance Modeling for Architectural Exploration of MPSoCs
Christian Haubelt
- 01 Jan 2009
TL;DR: In this paper, the authors propose an approach based on a SystemCsimulation framework and allow for evaluating timing effects from resource contention when mapping applica-tions to MPSoC platforms.
34
Task Migration in Mesh NoCs over Virtual Point-to-Point Connections
B. Goodarzi,Hamid Sarbazi-Azad +1 more
- 09 Feb 2011
TL;DR: This paper proposes an efficient methodology based on virtual point-to-point (VIP for short) connections that provides low-latency and low-power paths for heavy communication flows created by task migration mechanisms in NoCs.
23
Using task migration to improve non-contiguous processor allocation in NoC-based CMPs
TL;DR: Virtual point-to-point circuits are used, a state-of-the-art fast on-chip connection designed for network-on-chips, to virtually connect the disjoint regions and make the communication latency/power closer to the values offered by contiguous allocation schemes.
20
Applying autonomic principles for workload management in multi-core systems on chip
Johannes Zeppenfeld,Andreas Herkersdorf +1 more
- 14 Jun 2011
TL;DR: It is shown how monitors can be added to quantify the operating state of a typical processor core, whereupon a learning classifier system evaluator can determine appropriate actions to be performed in order to optimize the frequency and task distribution across the system.
16
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