Patent
Dynamic memory controller for single-chip microprocessor
Michael Gdula
- 25 Jul 1983
91
TL;DR: In this article, a controller for interfacing a single-chip microcomputer with external dynamic random access memory, including a subcircuit for generating a column-address strobe at a time after a row address strobe is generated, and also includes a multiplexing subcircuits for providing the proper 8-bit portion of a 16-bit address output from the microprocessor to the 8bit dynamic memory inputs, prior to receipt of the associated row-address or column address strobes.
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Abstract: A controller for interfacing a single-chip microcomputer with external dynamic random-access memory, includes a subcircuit for generating a column-address strobe at a time after a row-address strobe is generated, and also includes a multiplexing subcircuit for providing the proper 8-bit portion of a 16-bit address output from the microprocessor to the 8-bit dynamic memory inputs, prior to receipt of the associated row-address or column-address strobe. The microprocessor utilizes the strobe-generation and multiplexing subcircuits to burst-refresh the dynamic memory, in one presently preferred embodiment. In another presently preferred embodiment, lines from an additional microprocessor output port are utilized with a resettable binary counter and a multiplicity of buffers, to count through the range of row addresses in cyclic fashion, with each address being incremented after the previously-addressed row of memory cells has been refreshed.
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Citations
Patent
Integrated circuit I/O using a high performance bus interface
Michael Farmwald,Mark Horowitz +1 more
- 16 Apr 1991
TL;DR: In this article, the authors present a memory subsystem comprising at least two semiconductor devices (15, 16, 17), including at least one memory device connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address.
552
Patent
Method and apparatus for execution of operations in a flash memory array
Mickey L. Fandrich,Richard J. Durante,Keith F. Underwood,Rodney R. Rozman +3 more
- 30 Jun 1993
TL;DR: A flash memory system includes a user interface and array controller as discussed by the authors, where the user interface receives the user command issued by the processor and has the ability to queue a plurality of commands for execution.
228
Patent
Apparatus for synchronously generating clock signals in a data processing system
Michael Farmwald,Mark Horowitz +1 more
- 05 Mar 1992
TL;DR: In this paper, an apparatus for synchronously generating a first clock signal and a second clock signal in a second circuitry of a data processing system is described, where a clock generating circuitry generates a global clock signal.
227
Patent
Single-chip microcomputer
Shumpei Kawasaki,Yasushi Akao,Kouki Noguchi,Atsushi Hasegawa,Hiroshi Ohsuga,Keiichi Kurakazu,Kiyoshi Matsubara,Akio Hayakawa,Yoshitaka Ito +8 more
- 10 Aug 1994
TL;DR: In an evaluation single-chip microcomputer which includes circuit elements connected to an internal bus and capable of storing data or of arithmetic operation, the contents of the circuit elements being required to be known outside of the microcomputer, a control circuit decodes instructions supplied through theInternal bus and produces control signals for controlling the operations of the Circuit elements.
203
Patent
Memory circuitry having bus interface for receiving information in packets and access time registers
Michael Farmwald,Mark A. Horowitz +1 more
- 05 Mar 1992
TL;DR: In this article, an interfacing circuitry for a semiconductor circuit of a computer system selects the semiconductor circuits for a device operation in accordance with data, addresses, and control information received from a multiline bus of the computer system in a form of packets.
149
References
Patent
Single chip MOS computer with expandable memory
Henry M. Blume,David A. Stamm,David L. Budde +2 more
- 13 Feb 1978
TL;DR: In this article, an MOS digital computer incorporated on a single chip (monolithic structure) which includes a central processing unit (CPU), random access memory (RAM), and a programmable read-only memory (PROM).
80
Patent
Refresh system for dynamic RAM memory
Narendra Madhav Patel
- 08 Jan 1979
TL;DR: In this paper, a method and apparatus for controlling the refreshing of a volatile memory is disclosed in which conflicts between a memory refresh operation, the requirements for access to the memory during a data processing operation and a power up or power down condition are resolved.
56
Patent
Dynamic memory refresh system with additional refresh cycles
Michael Thaler
- 24 Jun 1980
TL;DR: In this paper, the enabling of a refresh cycle for a dynamic memory chip at a period in the fetch cycle, for example, of a type 8085 microprocessor, when the normal timing of the chip does not permit addressing of the memory.
10