Dynamic Hardware Development
Stephen Craven,Peter Athanas +1 more
TL;DR: This paper discusses the creation of a high-level development environment for reconfigurable designs that leverage an existing high- level synthesis tool to enable the design, simulation, and implementation of dynamically reconfiguring hardware solely from a specification written in C.
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Abstract: Applications that leverage the dynamic partial reconfigurability of modern FPGAs are
few, owing in large part to the lack of suitable tools and techniques to create them. While
the trend in digital design is towards higher levels of design abstractions, forgoing hardware
description languages in some cases for high-level languages, the development of a reconfigurable
design requires developers to work at a low level and contend with many poorly
documented architecture-specific aspects. This paper discusses the creation of a high-level
development environment for reconfigurable designs that leverage an existing high-level synthesis
tool to enable the design, simulation, and implementation of dynamically reconfigurable
hardware solely from a specification written in C. Unlike previous attempts, this approach
encompasses the entirety of design and implementation, enables self-re-configuration
through an embedded controller, and inherently handles partial reconfiguration. Benchmarking
numbers are provided, which validate the productivity enhancements this approach
provides.
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Citations
Automatic floorplanning and interface synthesis of island style reconfigurable systems with GOAHEAD
Christian Beckhoff,Dirk Koch,Jim Torreson +2 more
- 19 Feb 2013
TL;DR: A novel floorplanning algorithms that is based on an initial placement proposal created by the Xilinx vendor placer are introduced that are built-in in the tool GoAhead.
26
DAPR: Design Automation for Partially Reconfigurable FPGAs.
Shaon Yousuf,Ann Gordon-Ross +1 more
- 01 Jan 2010
TL;DR: This paper presents a PR design flow and associated tool to automate PR design intricacies and design space exploration and can significantly reduce PR design time effort and make PR designs more accessible and amenable to a wider range of PR designers.
17
Discrete wavelet transform realisation using run-time reconfiguration of field programmable gate array (FPGA)s
TL;DR: Three different hardware architectures for implementing multiple wavelet kernels for discrete wavelet transform are presented and FPGA synthesis results for simultaneous implementation of six different wavelets for the proposed methods are presented.
11
•Dissertation
Rapid Radio: Analysis-Based Receiver Deployment
Suris Pietri,Jorge Alberto +1 more
- 07 Aug 2009
5
Formulation-level design space exploration for partially reconfigurable FPGAs
Rohit Kumar,Ann Gordon-Ross +1 more
- 01 Dec 2011
TL;DR: This paper presents the first, to the best of the authors' knowledge, formulation-level PR DSE tool — FoRSE, which leverages the application's PR-architecture and mathematical FPGA device models and vendor-specified PR technology to generate Pareto-optimal sets of PR-floorplans and devices based on designer-designated implementation metrics.
5
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