Proceedings Article10.1145/513918.514041
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
Mohab Anis,M. A. Mahmoud,Mohamed I. Elmasry,Shawki Areibi +3 more
- 10 Jun 2002
- pp 480-485
TL;DR: Two techniques for efficient gate clustering in MTCMOS circuits by modeling the problem via Bin-Packing and Set-Partitioning techniques, which offer significant reduction in both dynamic and leakage power over previous techniques during the active and standby modes respectively are presented.
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Abstract: Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power dissipation. This paper presents two techniques for efficient gate clustering in MTCMOS circuits by modeling the problem via Bin-Packing (BP) and Set-Partitioning (SP) techniques. An automated solution is presented, and both techniques are applied to six benchmarks to verify functionality. Both methodologies offer significant reduction in both dynamic and leakage power over previous techniques during the active and standby modes respectively. Furthermore, the SP technique takes the circuit's routing complexity into consideration which is critical for Deep Sub-Micron (DSM) implementations. Sufficient performance is achieved, while significantly reducing the overall sleep transistors' area. Results obtained indicate that our proposed techniques can achieve on average 90% savings for leakage power and 15% savings for dynamic power.
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Citations
Robustness Issues of Run-time Leakage Control in Nano-scale Technologies
Danni Shi
- 01 Jan 2010
TL;DR: This thesis takes RBB as the target leakage reduction technique and analyzes the circuit response during mode transitions, including ground bounce magnitude and wake up time, and develops an accurate circuit model where on-chip and package parasitic parameters are added to ensure accuracy.
An effective power mode transition technique in MTCMOS circuits
Afshin Abdollahi,Farzan Fallah,Massoud Pedram +2 more
- 13 Jun 2005
TL;DR: Simulation results show that, compared to existing wakeup scheduling methods, the proposed techniques result in a one to two orders of magnitude improvement in the product of the maximum ground current and the wake up time.
Dynamic voltage and frequency scaling circuits with two supply voltages
W.H. Cheng,Bevan M. Baas +1 more
- 18 May 2008
TL;DR: Circuits that enable dynamic voltage and frequency scaling (DVFS) for fine-grained chip multi-processors to reduce both dynamic and leakage power dissipation are presented.
Bespoke Processors for Applications with Ultra-low Area and Power Constraints
Hari Cherupalli,Henry Duwe,Weidong Ye,Rakesh Kumar,John Sartori +4 more
- 24 Jun 2017
TL;DR: A case is made for bespoke processor design, an automated approach that tailors a general purpose processor IP to a target application by removing all gates from the design that can never be used by the application.
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TL;DR: This paper proposes a methodology for sizing the sleep transistor for a large module based on mutual exclusive discharge patterns of internal blocks that will give an upper bound for theSleep transistor size required to meet any performance constraint.
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
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TL;DR: To overcome the complexity of state dependence in average leakage estimation, the concept of "dominant leakage states" and use state probabilities are introduced and this accurate estimation is used in a new sensitivity-based leakage and performance optimization approach for circuits using dual V/sub t/ processes.