Proceedings Article10.1145/513918.514041
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
Mohab Anis,M. A. Mahmoud,Mohamed I. Elmasry,Shawki Areibi +3 more
- 10 Jun 2002
- pp 480-485
TL;DR: Two techniques for efficient gate clustering in MTCMOS circuits by modeling the problem via Bin-Packing and Set-Partitioning techniques, which offer significant reduction in both dynamic and leakage power over previous techniques during the active and standby modes respectively are presented.
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Abstract: Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power dissipation. This paper presents two techniques for efficient gate clustering in MTCMOS circuits by modeling the problem via Bin-Packing (BP) and Set-Partitioning (SP) techniques. An automated solution is presented, and both techniques are applied to six benchmarks to verify functionality. Both methodologies offer significant reduction in both dynamic and leakage power over previous techniques during the active and standby modes respectively. Furthermore, the SP technique takes the circuit's routing complexity into consideration which is critical for Deep Sub-Micron (DSM) implementations. Sufficient performance is achieved, while significantly reducing the overall sleep transistors' area. Results obtained indicate that our proposed techniques can achieve on average 90% savings for leakage power and 15% savings for dynamic power.
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Citations
Patent
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