Double patterning layout decomposition for simultaneous conflict and stitch minimization
Kun Yuan,Jae-Seok Yang,David Z. Pan +2 more
- 29 Mar 2009
- pp 107-114
TL;DR: This paper proposes a simultaneous conflict and stitch minimization algorithm with an integer linear programming (ILP) formulation that can reduce 33% of stitches and remove conflicts by 87.6% compared with two phase greedy decomposition.
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Abstract: Double patterning lithography (DPL) is considered as a most likely solution for 32nm/22nm technology. In DPL, the layout patterns are decomposed into two masks (colors). Two features (polygons) have to be assigned opposite colors if their spacing is less than certain minimum coloring distance. However, a proper coloring is not always feasible because two neighboring patterns within the minimum distance may be in the same mask due to complex pattern configurations. In that case, a feature may be split into two parts to resolve the conflict but the resulting stitch causes yield loss due to overlay error and increases manufacturing cost. While previous layout decomposition approaches perform coloring and splitting separately, in this paper, we propose an algorithm to minimize the number of conflicts and stitches simultaneously. Our algorithm is based on grid layout model and integer linear programming. Two techniques, independent component computation and layout partition, are proposed to reduce runtime of the algorithm. The experimental results show that, compared with the two phase decomposition flow, the proposed algorithm reduces the conflicts significantly using less stitches under reasonable runtime.
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Citations
Layout Decomposition Approaches for Double Patterning Lithography
Andrew B. Kahng,Chul-Hong Park,Xu Xu,Hailong Yao +3 more
- 01 Jun 2010
TL;DR: Experimental results show that the proposed layout decomposition approaches effectively decompose given layouts to satisfy the key goals of minimized line-ends and maximized overlap margin.
Design for Manufacturing With Emerging Nanolithography
TL;DR: This paper surveys key design for manufacturing issues for extreme scaling with emerging nanolithography technologies, including double/multiple patterning lithography, extreme ultraviolet lithographic, and electron-beam lithography.
127
An efficient layout decomposition approach for triple patterning lithography
Jian Kuang,Evangeline F. Y. Young +1 more
- 29 May 2013
TL;DR: This paper proposes an efficient layout decomposition approach for TPL, with the objective to minimize the number of conflicts and stitches, and finds that the whole layout can be reduced into several types of small feature clusters.
120
A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography
Jae-Seok Yang,Katrina Lu,Minsik Cho,Kun Yuan,David Z. Pan +4 more
- 18 Jan 2010
TL;DR: This paper proposes a multi-objective min-cut based decomposition framework for stitch minimization, balanced density, and overlay compensation, simultaneously, and shows that the proposed framework is highly scalable and fast.
References
Pitch doubling through dual-patterning lithography challenges in integration and litho budgets
Mircea Dusa,John Quaedackers,Olaf F. A. Larsen,Jeroen Meessen,Eddy van der Heijden,Gerald Dicker,Onno Wismans,Paul de Haas,Koen van Ingen Schenau,Jo Finders,Bert Vleeming,Geert Storms,Patrick Jaenen,Shaunee Cheng,Mireille Maenhoudt +14 more
TL;DR: A new CDU model was introduced to calculate double patterning budgets based on defining CD from its edges and pooling CD variance from two adjacent patterns within 2*Pitch distance, which achieved an experimental resolution of 32-nm 1/2 pitch on 1.2NA lithography system.
287
Layout decomposition for double patterning lithography
Andrew B. Kahng,Chul-Hong Park,Xu Xu,Hailong Yao +3 more
- 10 Nov 2008
Abstract: In double patterning lithography (DPL) layout decomposition for 45 nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum coloring spacing [11, 9, 5]. However, there exist pattern configurations for which pattern features separated by less than the minimum color spacing cannot be assigned different colors. In such cases, DPL requires that a layout feature be split into two parts. We address this problem using a layout decomposition algorithm that includes graph construction, conflict cycle detection, and node splitting processes. We evaluate our technique on both real-world and artificially generated test cases in 45 nm technology. Experimental results show that our proposed layout decomposition method effectively decomposes given layouts to satisfy the key goals of minimized line-ends and maximized overlap margin. There are no design rule violations in the final decomposed layout.
210
Issues and challenges of double patterning lithography in DRAM
Seo-Min Kim,Sunyoung Koo,Jaeseung Choi,Young-Sun Hwang,Jungwoo Park,Eung-Kil Kang,Chang-Moon Lim,Seung-Chan Moon,Jinwoong Kim +8 more
TL;DR: 37nm DRAM layout can be patterned and the overlay control and cost still remain as dominant obstacles, and the aggressive layout decomposition should be designed to solve the difficulty in core patterning.
181
22nm half-pitch patterning by CVD spacer self alignment double patterning (SADP)
TL;DR: In this article, a positive tone (spacer as mask) approach was used to create 22nm line and space arrays, on 300mm wafers, with full wafer critical dimension uniformity (CDU) < 2nm (3 sigma) and line edge roughness (LER) > 2nm.
167
Layout Decomposition Approaches for Double Patterning Lithography
Andrew B. Kahng,Chul-Hong Park,Xu Xu,Hailong Yao +3 more
- 01 Jun 2010
TL;DR: Experimental results show that the proposed layout decomposition approaches effectively decompose given layouts to satisfy the key goals of minimized line-ends and maximized overlap margin.
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