Patent
Distributed serialized data buffer and a memory module for a cascadable and extended memory subsystem
Paul W. Coteus,Daniel M. Dreps,Charles A. Kilmer,Kyu-hyoun Kim,Warren E. Maule,Todd E. Takken +5 more
- 22 Oct 2015
4
TL;DR: In this paper, the authors describe techniques for routing data through one or more cascaded memory modules, where each memory module can include a plurality of data buffers, and each data buffer includes ports for routing to and/or from other memory modules.
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Abstract: Embodiments disclosed herein generally relate to techniques for routing data through one or more cascaded memory modules. Each memory module can include a plurality of data buffers. Each data buffer includes a plurality of ports for routing data to and/or from other memory modules. In one embodiment, the data buffer is configured to route write data to DRAM devices on a first memory module or route write data to a data buffer of at least one downstream memory module. The data buffer is also configured to receive read data from a DRAM device of the first memory module or receive read data from a downstream memory module.
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Citations
Patent
Memory device and refresh method for PSRAM
Hou Chien-Ti,Tu Ying-Te +1 more
- 05 Mar 2020
TL;DR: In this article, a memory device consisting of a pseudo static random access memory (PSRAM), a word line (WL) arbitrator and a refresh controller is provided, where the WL arbitrator receives a WL signal and segments it according to a burst length setting value.
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Patent
Memory module and memory system including the same
Kim Kwan-Dong
- 01 Jan 2019
TL;DR: In this article, a memory module includes memory devices; data buffers suitable for receiving write data transferred from a memory controller and transmitting read data to the memory controller; a buffer control signal generation circuit suitable for generating buffer control signals for controlling the data buffers, by using a command transferred from the memory controllers; a command delay circuit, which delays the execution of a command by a delay amount of the buffer controller signal in a read operation and a write operation.
2
Patent
High-performance on-module caching architectures for non-volatile dual in-line memory module (NVDIMM)
Amin Farmahini Farahani,David A. Roberts +1 more
- 06 Aug 2019
TL;DR: In this paper, a high-performance on-module caching architecture for hybrid memory modules is presented, which includes a cache controller, a volatile memory tag unit coupled to the cache controller.
1
Patent
Memory module and memory system including same
Kim Kwan-Dong
- 07 Dec 2018
TL;DR: In this article, a memory module includes memory devices; data buffers suitable for receiving write data transferred from a memory controller and transmitting read data to the memory controller; a buffer control signal generation circuit suitable for generating buffer control signals for controlling the data buffers, by using a command transferred from the memory controllers; a command delay circuit, which delays the execution of a command by a delay amount of the buffer controller signal in a read operation and a write operation.
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Rajamani Ramasubramanian
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Yoshinori Matsui
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TL;DR: In this article, a memory system consisting of a memory controller and a memory module mounted with DRAMs is proposed to reduce the influence of reflection signals caused by branching and impedance mismatching in various wirings.
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Patent
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TL;DR: A dual-inline memory module (DIMM) includes a card having a length of about 151.2 to 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to a card, the buffer device configured for converting a packetized memory interface.
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Patent
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