Patent
Disabling a command associated with a memory device
Christopher P. Mozak,Kuljit S. Bains +1 more
- 25 Nov 2015
10
TL;DR: In this article, a memory device may contain device processing logic and a mode register, a register that may specify a mode of operation of the memory device, and a field in the mode register may hold a value that may indicate whether a command associated with the memory devices is disabled.
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Abstract: In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation of the memory device. A field in the mode register may hold a value that may indicate whether a command associated with the memory device is disabled. The value may be held in the field until either the memory device is power-cycled or reset. The device processing logic may acquire an instance of the command. The device processing logic may determine whether the command is disabled based on the value held by the mode register. The device processing logic may not execute the instance of the command if the device processing logic determines the command is disabled. If the device processing logic determines the command is not disabled, the device processing logic may execute the instance of the command.
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Citations
Patent
Soft post package repair of memory devices
Alan J. Wilson,Jeffrey P. Wright +1 more
- 19 Apr 2016
TL;DR: In this paper, a soft post package repair system is described, which can include memory cells in a package, volatile memory configured to store defective address data responsive to entering soft post-package repair mode, a match logic circuit and a decoder.
20
Patent
Apparatuses and methods to perform post package trim
Alan J. Wilson,Jeffrey P. Wright +1 more
- 09 Nov 2015
TL;DR: In this paper, apparatuses and methods to perform post package trimming of memory die, which advantageously permits the memory die to be trimmed after the memory dies are stacked, such that test and trimming characteristics are relatively close to that which will be actually be encountered.
6
Patent
Memory device performing post package repair (ppr) operation
Seong-Jin Lee,Ju-Yun Jung,Yoo-Jung Lee +2 more
- 08 Nov 2016
TL;DR: In this paper, a memory device including; a memory cell array including memory cells connected to word lines and bit lines, and redundancy memory cells connecting to a redundancy word line and the bit lines is configured to control execution of a post package repair operation.
4
Patent
Methods and systems for analyzing record and usage in post package repair
Feng-Chou Wu
- 06 Apr 2017
TL;DR: In this paper, the PPR status of dual-in-line memory modules (DIMMs) of a server system is tracked using a controller (e.g., BMC).
3
Patent
Dynamic regulation method and device for signal quality of I2C bus
Wang Zhihao
- 27 Oct 2017
TL;DR: In this paper, a dynamic regulation method and device for signal quality of an I2C bus is presented, which comprises the steps that 1, whether the bus capacitance or pull-up resistance of the I2c bus exceeds a preset range is judged, wherein the preset range was defined in a standard and 2, if yes, the value of the bus or pullup resistance exceeding the preset ranges is obtained dynamically, so that the bus capacity or the pullup resistances are within a specified preset range.
2
References
Patent
Memory device having circuitry for initializing and reprogramming a control operation feature
Brett L. Williams,Schaefer Scott E +1 more
- 13 Jan 1997
TL;DR: A synchronous dynamic random access memory (SDRAM) device has a master control circuit for accepting a first command and a second command and having an initialization and reprogramming circuit as discussed by the authors.
67
Patent
Method and system for error management in a memory device
Kuljit S. Bains,David J. Zimmerman,Dennis W. Brzezinski,Michael W. Williams,John B. Halbert +4 more
- 09 Dec 2009
TL;DR: In this article, a method and system for error management in a memory device is presented, where the memory device can handle commands and address parity errors and cyclic redundancy check errors.
53
Patent
Integrated circuit memory devices that support selective mode register set commands and related memory modules, memory controllers, and methods
Kee-Hoon Lee,Changsik Yoo,Kye-Hyun Kyung +2 more
- 11 Aug 2004
TL;DR: In this paper, a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode-register-set operation is discussed.
52
Patent
Circuit and method for test and repair
Timothy B. Cowles,Christian N. Mohr +1 more
- 15 Mar 2001
TL;DR: In this article, a preferred embodiment of the current invention concerns memory testing and repair processes, wherein circuitry is provided to allow on-chip comparison of stored data and expected data, where the tester can transmit in a parallel manner the expected data to a plurality of chips.
47
Patent
Selective application of program inhibit schemes in non-volatile memory
Jun Wan,Jeffrey W. Lutze,Masaaki Higashitani,Gerrit Jan Hemink,Ken Oowada,Jian Chen,Geoffrey S. Gongwer +6 more
- 11 May 2006
TL;DR: In this paper, a non-volatile memory system is programmed so as to reduce or avoid program disturb, and a program inhibit scheme is selected based on the word line being programmed.
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