Patent
Digital processing circuit having a multiplication function
Toshiaki Machida
- 25 Feb 1982
59
TL;DR: In this article, the multiplicand and the multiplier are multiplied by each other to produce a partial product, and the obtained partial products are added to the sum of previously obtained products.
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Abstract: In a Booth's algorithm multiplication circuit, a multiplicand is set in a multiplication register and a multiplier is set in a multiplier shift-register. Consecutive bits of the multiplier are applied to a Booth's decoder to produce coefficients, and the multiplicand and coefficient are multiplied by each other to produce a partial product. Partial products are produced for every three consecutive bits of the multiplier, and the obtained partial products are added to the sum of previously obtained partial products. After all the partial products are added together, the resultant sum is derived from the adder or from the feed-back path of the output from the adder.
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Citations
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George Landers,Earle W. Jennings,Tim B. Smith,Glen Haas +3 more
- 20 Jan 1998
TL;DR: In this paper, a reconfigurable processor includes at least three (3) MacroSenquencers (10-16) which are configured in an array, each of which is operable to receive on a separate one of four buses (18) an input from other three MacroSequencers and from itself in a feedback manner.
159
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Koji Kuroda,Shoji Nakatani +1 more
- 21 Nov 1988
TL;DR: In this paper, a multiplicand data and a multiplier data are combined in a regular multiplication mode to produce a population counting result for the input data is obtained and output, and the partial counted data is sent to a carry save adder and a carry propagate adder.
110
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Fixed-point multiplier-accumulator architecture
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TL;DR: In this article, an integrated circuit multiplier-accumulator architecture includes an M-bit wide register for inputting an X operand to a multiplier and an N-bit input register for outputting a Y operand.
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Asynchronous high speed processor having high speed memories with domino circuits contained therein
Michael J. Cochran
- 11 Apr 1984
TL;DR: In this article, the minimum possible delay time is implemented through the providing a completion pulse upon the completion of each operation and initiating a subsequent operation at the receipt of the completion pulse.
40
References
Patent
High speed combinatorial digital multiplier
Robert C. Ghest,Hua-Thye Chua,John M. Birkner +2 more
- 18 Aug 1977
TL;DR: In this paper, a high speed 8 by 8 digital multiplier was proposed for implementation on a single semiconductor chip including an encoder for implementing the Modified Booth Algorithm to encode the eight multiplier digits.
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Patent
Arithmetic unit for use in data processing systems
Blau Jonathan S,Rosen Josh +1 more
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TL;DR: In this paper, a data processing system using unique procedures for handling various arithmetic operations is presented, where a look-ahead carry bit generator stage is used for such purpose to reduce the overall mantissa calculation time.
47
Speech synthesis integrated circuit device
TL;DR: In this paper, an integrated circuit device or chip which digitally synthesizes human speech using a linear predictive filter is described. But, this device may be implemented using conventional processing techniques, such as P-channel MOS technology.
34
Patent
Serial-parallel multiplier using booth{3 s algorithm with combined carry-borrow feature
Ghest Robert C,Springer John S +1 more
- 30 Nov 1973
TL;DR: In this article, a high speed hardware digital cell is used in an iterative array for multiplication of signed and unsigned numbers, where the multiplier takes the whole multiplicand in parallel and utilizes a single bit at a time of the multiplier to form partial products using the same logic gates to store both carry and borrow bit information which is utilized in add/subtract and shift multiplication.
13
Patent
Microprocessor having multiply/divide circuitry
George P. Chamberlin
- 25 Sep 1978
TL;DR: In this paper, a microprocessor with the capability of performing either a multiply or divide operation from a single instruction for each operation is described, and a shift and add algorithm is used for multiplication while for division a non-restoring divide algorithm was used.
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