Device interface controller for intercepting communication between a microcomputer and peripheral devices to control data transfers

TL;DR: In this paper, an intelligent direct memory access (DMA) controller interprets user commands from a host system, translates virtual addresses from the user applications program to physical addresses, and retrieves blocks of data from the main system memory at the request of the user's code, rather than at the permission of the kernel code of the host system.

TL;DR: In this paper, the authors propose a fault tolerant execution of an application program in a server network, which includes: a first server for executing the application program; a cluster network database coupled to the first server; an object, stored in the cluster database, which represents the program and contains information pertaining to the program.

TL;DR: In this article, a network of microcontrollers for monitoring and diagnosing the environmental conditions of a computer is disclosed, which allows users to replace failed components, and add new functionality, such as new network interfaces, disk interface cards and storage, without impacting existing users.

TL;DR: In this article, a transducer is coupled with a transceiver for sensing a process variable and outputting the output of the transducers to the transmitter. But the transmitter interface circuitry is adapted to couple to a process control loop which operates in accordance with the Fieldbus standard.

TL;DR: In this paper, the authors propose an interleaving mechanism for concurrent performance of two different modes of data transfer between the host processor and the I/O controller, which enables host processor direct program control (DPC) data transfers to be performed at the same time that the controller is busy doing cycle steal data transfers for a block of data.

TL;DR: In this paper, the memory bus means are configurated to allow direct data transfer between any memory fraction of central processing unit systems without interfering with the central processing units that being controlled by direct memory access control means.

TL;DR: A disk address controller as mentioned in this paper is a random access memory for storing the upper and lower limit addresses of the access area of each of processing units which are allotted to a disk unit, and storing the disk address specified by a disk input/output instruction from the processing unit.

TL;DR: In this article, a data proessing system includes a processor, a memory, a direct memory accessing (DMA) control unit and an input/output adapter, and a memory area of a given capacity is reserved in the memory for storing control information transferred between the processor and the adapter.