Deterministic test pattern generation techniques for sequential circuits
Ilker Hamzaoglu,Janak H. Patel +1 more
- 05 Nov 2000
- pp 538-543
TL;DR: A new ATPG system for sequential circuits, called ATOMS, is developed and a new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation algorithms are presented.
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Abstract: This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation algorithms. To be able to assess the effectiveness of the proposed techniques, we have developed a new ATPG system for sequential circuits, called ATOMS, and we have incorporated these techniques into the test generator. ATOMS achieved very high fault coverages in a short amount of time for the ISCAS89 sequential benchmark circuits, demonstrating the effectiveness of these techniques on the test generation performance.
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Citations
ML-Based Fault Injection for Autonomous Vehicles: A Case for Bayesian Fault Injection
Saurabh Jha,Subho S. Banerjee,Timothy Tsai,Siva Kumar Sastry Hari,Michael J. Sullivan,Zbigniew Kalbarczyk,Stephen W. Keckler,Ravishankar K. Iyer +7 more
- 24 Jun 2019
TL;DR: DriveFI is presented, a machine learning-based fault injection engine, which can mine situations and faults that maximally impact AV safety, as demonstrated on two industry-grade AV technology stacks (from NVIDIA and Baidu).
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•Posted Content
ML-based Fault Injection for Autonomous Vehicles: A Case for Bayesian Fault Injection
Saurabh Jha,Subho S. Banerjee,Timothy Tsai,Siva Kumar Sastry Hari,Michael J. Sullivan,Zbigniew Kalbarczyk,Stephen W. Keckler,Ravishankar K. Iyer +7 more
TL;DR: In this paper, a machine learning-based fault injection engine, called DriveFI, was proposed to mine situations and faults that maximally impact AV safety, as demonstrated on two industry-grade AV technology stacks (from NVIDIA and Baidu).
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On random pattern generation with the selfish gene algorithm for testing digital sequential circuits
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TL;DR: The spectral method of sequential circuit test generation is enhanced by using a selfish gene algorithm that can outperform the previously-published spectral method in either fault coverage, or shorter vector length, or both.
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State variable extraction to reduce problem complexity for ATPG and design validation
Qingwei Wu,Michael S. Hsiao +1 more
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References
Combinational profiles of sequential benchmark circuits
F. Brglez,D. Bryan,K. Kozminski +2 more
- 08 May 1989
TL;DR: A set of 31 digital sequential circuits described at the gate level that extend the size and complexity of the ISCAS'85 set of combinational circuits and can serve as benchmarks for researchers interested in sequential test generation, scan-basedtest generation, and mixed sequential/scan-based test generation using partial scan techniques.
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An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
TL;DR: PODEM (path-oriented decision making) is a new test generation algorithm for combinational logic circuits that uses an implicit enumeration approach analogous to that used for solving 0-1 integer programming problems and is significantly more efficient than DALG over the general spectrum of combinational Logic circuits.
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HITEC: a test generation package for sequential circuits
Thomas M. Niermann,Janak H. Patel +1 more
- 25 Feb 1991
TL;DR: HITEC is presented, a sequential circuit test generation package to generate test patterns for sequential circuits, without assuming the use of scan techniques or a reset state, and several new techniques are introduced to improve the performance of test generation.
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PROOFS: a fast, memory-efficient sequential circuit fault simulator
TL;DR: The authors describe PROOFS, a fast fault simulator for synchronous sequential circuits that achieves high performance by combining all the advantages of differential fault simulation, single fault propagation, and parallel fault simulation while minimizing their individual disadvantages.
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Test generation for sequential circuits
TL;DR: The deterministic sequential test-generation algorithm, based on extensions to the PODEM justification algorithm, is effective for midsized sequential circuits and can be used in conjunction with an incomplete scan design approach to generate tests for very large sequential circuits.
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