Open AccessJournal Article
Deterministic seed selection and pattern reduction in logic BIST
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TL;DR: A new ad-hoc technique to select the proper seed and the number of the random test patterns to be generated is presented and it is shown that this scheme produces the same fault coverage with lesser number ofrandom test patterns than an arbitrary seed.
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Abstract: A new ad-hoc technique to select the proper seed and the number of the random test patterns to be generated is presented. This technique uses an offline algorithm to search and classify the random patterns based on the deterministic test patterns generated by the automatic test pattern generator (ATPG). The seed activated linear feedback shift register (LFSR) generates exhaustive test patterns which are applied on any design under test (DUT). The responses are received at the output of the scan chains in the DUT and they are compressed to produce a signature. It is shown that this scheme produces the same fault coverage with lesser number of random test patterns than an arbitrary seed. Also, this technique helps to estimate the number of BIST test patterns to be generated to achieve specific fault coverage. Results on six ISCAS-89 designs with the help of Cadence Encounter true time 13.1 ATPG is shown.
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Citations
Design of reconfigurable LFSR for VLSI IC testing in ASIC and FPGA
K. N. Devika,Ramesh Bhakthavatchalu +1 more
- 06 Apr 2017
TL;DR: The design of a reconfigurable Linear Feedback Shift Register (LFSR) for Very Large Scale Integration (VLSI) Integrated Circuit (IC) testing and four structural representations such as Modular, Standard, Hybrid and Complete LFSR are implemented.
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Programmable MISR modules for logic BIST based VLSI testing
K. N. Devika,Ramesh Bhakthavatchalu +1 more
- 01 Dec 2016
TL;DR: This paper focus on the design of Programmable MISR(Multiple Input Signature Register) modules for Logic BIST based Very Large Scale Integration(VLSI) Integrated Circuit(IC) testing.
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Design and Analysis of Test Pattern Generator by combining internal and external LFSR
Chinnapapakkagari Sreenivasa Vikranth,Kanna Rakesh,Bodavula Jagadeesh,Doriginti Mohammad,Geethu Remadevi Somanathan,Ramesh Bhakthavatchalu +5 more
- 03 Jun 2021
TL;DR: In this article, a Test Pattern Generator is implemented which can work as internal and external LFSR based on the control signal, and the main objective of this work is to increase the length of the Pseudorandom sequences generated by a test pattern generator.
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Design of efficient programmable test-per-scan logic BIST modules
K. N. Devika,Ramesh Bhakthavatchalu +1 more
- 01 Aug 2017
TL;DR: This paper focus on the design of Programmable Logic BIST structures for Very Large Scale Integration (VLSI) Integrated Circuit(IC) testing and the results of the proposed programmable PRPG and MISR designs were analyzed for speed, power and area.
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Power analyzer of linear feedback shift register techniques using built in self test
K. Suriyan,Nagarajan Ramalingam,Kanagaraj Venusamy,Sathish Sivaraman,Kiruthiga Balasubramaniyan,Manjunathan Alagarsamy +5 more
TL;DR: In this paper , a built-in self-test (BIST) technique for scan-based circuits is proposed to save energy in the linear feedback shift register and circuit under examination in a random research region.
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Michael L. Bushnell,Vishwani D. Agrawal +1 more
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TL;DR: This book provides a careful selection of essential topics on all three types of circuits, namely, digital, memory, and mixed-signal, each requiring different test and design for testability methods.
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Improving Linear Test Data Compression
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TL;DR: The ideas proposed in this paper transform the output space of a linear decompressor so as to reduce the number of inputs required thereby increasing compression while still keeping all the test cubes in theoutput space.
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Test structure verification of logical BIST: problems and solutions
M. Cogswell,D. Pearl,J. Sage,A. Troidl +3 more
- 03 Oct 2000
TL;DR: A set of proven production level procedures used to identify and verify the test structure and behavior of BIST hardware are described, based on the TSV implementation of IBM's TestBench test generation system.
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