Proceedings Article10.1109/RECONFIG.2012.6416736
Design and analysis of layered coarse-grained reconfigurable architecture
Zoltan Endre Rakossy,T. Naphade,Anupam Chattopadhyay +2 more
- 01 Dec 2012
- pp 1-6
19
TL;DR: A novel CGRA where data access, data transport and execution are separately layered into dedicated, independent structures to address the storage access bottleneck, faced by state-of-the-art CGRAs.
read more
Abstract: Coarse-grained reconfigurable architectures (CGRAs) represent an important class of programmable accelerators with a significant performance advantage for data-driven, systolic algorithms. In this paper, we present a novel CGRA where data access, data transport and execution are separately layered into dedicated, independent structures. The proposed architecture concept allows for independent control and optimization on each layer to address the storage access bottleneck, faced by state-of-the-art CGRAs. The architecture is programmable and the implementation is derived from a high-level language specification, allowing fast design exploration, debugging and simulation. Up to 50% run-time performance improvement and 5× area-time-energy product gain of the layered CGRA over a non-layered one is demonstrated with 2 case studies from demanding linear algebra applications.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures
TL;DR: This paper makes two contributions: establishing a precise formulation for the CGRA mapping problem while using shared local data memory as a routing resource and extracting an effective approach for mapping loops to CGRAs.
46
Energy Challenges for ICT
Giorgos Fagas,John P. Gallagher,Luca Gammaitoni,Douglas J. Paul +3 more
- 22 Mar 2017
TL;DR: The challenges and opportunities in this emerging eld are introduced and a common framework to strive towards energy-sustainable ICT is introduced.
Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable Architectures
Alexander Fell,Zoltan Endre Rakossy,Anupam Chattopadhyay +2 more
- 01 Dec 2014
TL;DR: An algorithm is proposed that employs Force-Directed Scheduling concepts to solve such scheduling and resource minimization problems, and hisuristic extensions are flexible enough for generic heterogeneous CGRAs, allowing to estimate the execution time of an algorithm with different configurations, while maximizing the utilization of available hardware.
23
Efficient and scalable CGRA-based implementation of Column-wise Givens Rotation
Zoltan Endre Rakossy,Farhad Merchant,Axel Acosta-Aponte,S. K. Nandy,Anupam Chattopadhyay +4 more
- 18 Jun 2014
TL;DR: These algorithms allow annihilation of multiple elements in a column of the input matrix simultaneously, without a dependency bottle-neck allowing increased parallelism, resource sharing and scalability.
18
Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation
Zoltan Endre Rakossy,Farhad Merchant,Axel Acosta-Aponte,S. K. Nandy,Anupam Chattopadhyay +4 more
- 01 Oct 2014
TL;DR: A new layered reconfigurable architecture is proposed which exploits modularity, scalability and flexibility to achieve high energy efficiency and memory bandwidth and achieves a clean trade-off of execution speed versus area, while keeping relatively constant energy.
17
References
Baring it all to software: Raw machines
E. Waingold,Michael Taylor,Devabhaktuni Srikrishna,Vivek Sarkar,Whay S. Lee,Victor W. Lee,Jason Kim,Matthew I. Frank,P. Finch,Rajeev Barua,Jonathan Babb,Saman Amarasinghe,Anant Agarwal +12 more
TL;DR: The most radical of the architectures that appear in this issue are Raw processors-highly parallel architectures with hundreds of very simple processors coupled to a small portion of the on-chip memory, allowing synthesis of complex operations directly in configured hardware.
725
•Proceedings Article
MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources
Ethan Mirsky,AndrC DeHon +1 more
- 01 Jan 1996
TL;DR: MATRIX as discussed by the authors is a coarse-grained, reconfigurable com- puting architecture which supports confgurable instruction distribution, where device resources are allocated to control- ling and describing the computation on a per task basis.
MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources
TL;DR: MATRIX is a novel, coarse-grain, reconfigurable computing architecture which supports configurable instruction distribution that can serve as an instruction store, a memory element, or a computational element, and the adaptability is made possible by a multi-level configuration scheme.
440
The density advantage of configurable computing
TL;DR: The author attempts to answer questions as to why FPGAs have been so much more successful than their microprocessor and DSP counterparts and how configurable computing fits into the arsenal of structures used to build general, programmable computing platforms.
The Design of Optimal Systolic Arrays
Guo-Jie Li,Wah +1 more
TL;DR: In this paper, a methodology to systematically search and reduce this space and to obtain the optimal design is proposed, including matrix multiplication, finite impulse response filtering, deconvolution, and triangular matrix inversion.
252