Patent
Delay pulse generating circuit
Kenji Yoshida
- 20 Jul 1982
43
TL;DR: A delay signal generating circuit includes feedback loops and components for selectively setting the delay time of a delay unit in one of the loops as discussed by the authors, which can be used to provide an adjustable delay to a signal being propagated therethrough, and the delay unit can be bypassed.
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Abstract: A delay signal generating circuit includes feedback loops and components for selectively setting the delay time of a delay unit in one of the loops. The circuit can be used to provide an adjustable delay to a signal being propagated therethrough, and the delay unit can be bypassed.
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Citations
Patent
Phase-locked loop delay line
Karl M. J. Lofgren,Gerald W. Shearer,Kenneth W. Ouyang +2 more
- 03 Jun 1988
TL;DR: In this article, a phase-locked loop driven by a reference frequency source such as a crystal oscillator and including a variable delay circuit is proposed to provide precise delays. But the phase error signal representative of phase error is developed and applied to vary the amount of delay until the phase errors are eliminated.
176
Patent
Digital clock buffer circuit providing controllable delay
W. Daniel Hillis,Zahi S. Abuhamdeh,Bradley C. Kuszmaul,Shaw-Wen Yang,Jon Wade +4 more
- 19 Feb 1991
TL;DR: In this paper, a clock buffer circuit that generates a local clock signal in response to a system clock signal was proposed, where the buffer control circuit provides a variable delay so that the local clock signals have a selected phase relationship in relation to the system clock signals.
109
Patent
Delay control circuit
Steven S. Chan
- 11 Jan 1988
TL;DR: In this article, the propagation delay introduced by the components in the ring oscillator is determined by measuring the frequency of the output signal produced by the oscillator which provides a signal to a multiplexer which selects among a number of preset delay components.
88
Patent
Semiconductor Integrated circuit
Yutaka Shinagawa,Takeshi Kataoka,Eiichi Ishikawa,Toshihiro Tanaka,Kazumasa Yanagisawa,Kazufumi Suzukawa +5 more
- 17 Oct 2006
TL;DR: In this article, a semiconductor integrated circuit (SIC) has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the SIC.
76
Patent
Programmable capacitance delay element having inverters controlled by adjustable voltage to offset temperature and voltage supply variations
Christopher Koerner,Alberto Gutierrez,Edward Gary Pumphrey +2 more
- 01 Nov 1991
TL;DR: In this article, a delay element for fine tuning the position in time of timing edges of an input signal, comprising a first and a second inventer, each comprising a data input, a control input and a data output, is presented.
73
References
Patent
Automatic time control circuit
D Graziani
- 20 Jul 1971
TL;DR: In this paper, the time delay of an ADJUSTIFIRCUIT is attributed to an error VOLTAGE, which is derived from the continuuous comparison of the time DELAY with another time known as a CRYSTAL OSCILLATOR.
8