Patent
Decoupled processor instruction window and operand buffer
Douglas C. Burger,Aaron Smith,Jan Gray +2 more
- 26 Jun 2015
12
TL;DR: In this article, a processor core in an instruction block-based microarchitecture is configured so that an instruction window and operand buffers are decoupled for independent operation in which instructions in the block are not tied to resources such as control bits and operands that are maintained in the operand buffer.
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Abstract: A processor core in an instruction block-based microarchitecture is configured so that an instruction window and operand buffers are decoupled for independent operation in which instructions in the block are not tied to resources such as control bits and operands that are maintained in the operand buffers. Instead, pointers are established among instructions in the block and the resources so that control state can be established for a refreshed instruction block (i.e., an instruction block that is reused without re-fetching it from an instruction cache) by following the pointers. Such decoupling of the instruction window from the operand space can provide greater processor efficiency, particularly in multiple core arrays where refreshing is utilized (for example when executing program code that uses tight loops), because the operands and control bits are pre-validated.
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Citations
Patent
Reuse of decoded instructions
Douglas C. Burger,Aaron L. Smith +1 more
- 26 Jun 2015
TL;DR: In this paper, the authors present a system for reusing fetched and decoded instructions in block-based processor architectures, where the instruction scheduler can adjust a mapping of instruction blocks in flight so that the given instruction block is re-executed on the first processor core without re-fetching the given instructions.
15
Patent
Verifying branch targets
Douglas C. Burger,Aaron L. Smith,Jan Gray +2 more
- 26 Jun 2015
TL;DR: In this article, an approach and methods for implementing bad jump detection in block-based processor architectures are described. But they do not specify a specific implementation of the bad jump detector, only a control unit that checks whether a branch signal is received from one of the instruction blocks.
13
Patent
Mapping instruction blocks based on block size
Douglas C. Burger,Aaron Smith,Jan Gray +2 more
- 26 Jun 2015
TL;DR: A processor core in an instruction block-based microarchitecture utilizes instruction blocks having headers that include an index to a size table that may be expressed using one of memory, register, logic, or code stream as discussed by the authors.
10
Patent
Age-based management of instruction blocks in a processor instruction window
Douglas C. Burger,Aaron L. Smith,Jan Gray +2 more
- 26 Jun 2015
TL;DR: In this paper, a processor core in an instruction block-based microarchitecture includes a control unit that explicitly tracks instruction block state including age or priority for current blocks that have been fetched from an instruction cache.
10
Patent
Explicit instruction scheduler state information for a processor
Jan Gray,Doug Burger,Aaron L. Smith +2 more
- 26 Jun 2015
TL;DR: In this paper, a method for fetching a group of instructions, where the group is configured to execute atomically by a processor, is provided, and the method further includes scheduling at least one of the instructions for execution by the processor before decoding the others.
9
References
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ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix
Bingfeng Mei,Serge Vernalde,Diederik Verkest,Diederik Verkest,Hugo De Man,Rudy Lauwereins +5 more
- 01 Sep 2003
TL;DR: A novel architecture with tightly coupled very long instruction word (VLIW) processor and coarse-grained reconfigurable matrix is proposed, which has good performance and is very compiler-friendly.
674
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
Karthikeyan Sankaralingam,Ramadass Nagarajan,Haiming Liu,Changkyu Kim,Jaehyuk Huh,Doug Burger,Stephen W. Keckler,Charles R. Moore +7 more
- 01 May 2003
TL;DR: Results show that high performance can be obtained in each of the three modes--ILP, TLP, and DLP-demonstrating the viability of the polymorphous coarse-grained approach for future microprocessors.
Scaling to the end of silicon with EDGE architectures
Doug Burger,Stephen W. Keckler,Kathryn S. McKinley,Mike Dahlin,Lizy K. John,Calvin Lin,Charles R. Moore,Jim Burrill,Robert McDonald,W. Yoder +9 more
TL;DR: The TRIPS architecture is the first instantiation of an EDGE instruction set, a new, post-RISC class of instruction set architectures intended to match semiconductor technology evolution over the next decade, scaling to new levels of power efficiency and high performance.
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