Patent
Decoding method and apparatus having optimum decoding paths
Jechang Jeong,Hyun-Soo Shin +1 more
- 28 Mar 1994
3
TL;DR: In this paper, a decoding method and apparatus having an optimum decoding path includes a Viterbi decoder having an overlapping function in which the input signal is moved in units of the window movement distance of at least one symbol and the code sequence is decoded in units representing a decoding depth, so that overlap in the decoded data occurs.
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Abstract: A decoding method and apparatus having an optimum decoding path includes a Viterbi decoder having an overlapping function in which the input signal is moved in units of the window movement distance of at least one symbol and the code sequence is decoded in units representing a decoding depth, so that overlap in the decoded data occurs. Then, the output of the Viterbi decoder with the overlap function is stored in a memory. A control signal generator controls the positions of the data to be output from the memory according to the output of a counter receiving the decoded data. The most frequent data out of all data supplied to a comparator is selected as an optimum decoding path. Thus, the error associated with wrong path selection, e.g., when the data is wrongly decoded due to the error generated by the noise added during transmission, can be reduced.
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Citations
Patent
Method and apparatus for compensation of linear or nonlinear intersymbol interference and noise correlation in magnetic recording channels
Oscar Ernesto Agazzi,Nambirajan Seshadri +1 more
- 13 Dec 1995
TL;DR: In this paper, a concatenated decoder consisting of an inner decoder and a postprocessor is proposed for decoding a signal in the presence of linear or nonlinear interference, correlated noise or a combination thereof.
92
Patent
Viterbi decoding method and apparatus with balance among memory and processing requirements
Ono Shigeru,Hiroshi Katsuragawa +1 more
- 22 Jul 1996
TL;DR: In this article, a Viterbi decoding method and apparatus employ a path memory describing paths with a length of X·N branches, where N is a fixed positive integer, and X has a fixed value not less than two.
17
Patent
Low power viterbi decoder using a novel register-exchange architecture
Tuhin Subhra Chakraborty
- 12 Sep 2006
TL;DR: In this paper, an apparatus and method of reducing power dissipation in a register exchange implementation of a Viterbi decoder used in a digital receiver or mass-storage system without degrading the bit error rate of the decoder, by selectively inhibiting data samples in the register memory from being shifted if the data samples have converged to a single value.
4
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Gould Adam F,Arora Arvind S +1 more
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Patent
Distributed trellis encoder
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