Patent
Debugging system of parallel processing program and its debugging method
Yuji Sato,Norihisa Murayama +1 more
- 12 Feb 1999
2
TL;DR: In this article, a debugging system for a data parallel processor is presented, which performs debugging of plural parallel processes by means of corresponding serial debuggers 21-1, 21-2,..., and outputs their processing results as response information to a management process 18.
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Abstract: PROBLEM TO BE SOLVED: To provide a debugging system and its debugging method which efficiently perform debugging of a parallel processing program for a data parallel processor and which considerably contribute to program development support as an effective debugging tool for a parallel processing program method. SOLUTION: This is a debugging system for a data parallel processor which performs debugging of plural parallel processes 22-1, 22-2,..., by means respectively of corresponding serial debuggers 21-1, 21-2,..., and outputs their processing results as response information to a management process 18. Also, the process 18 knows an original reason of why response information is received, utilizes it as response information to a debugging command and manages the debugging state of each serial debugger.
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Citations
Patent
Apparatus and method for external access to core resources of a processor, semiconductor systems development tool comprising the apparatus, and computer program product and non-transitory computer-readable storage medium associated with the method
D. D. Popa,Alexandra Dracea,Dragos Miloiu +2 more
- 22 Nov 2013
TL;DR: In this paper, an apparatus for external access to core resources ( 211,212 ) of a processor comprising a processing core (21 ), a shared memory (22), and a multiple paths Direct Memory Access, DMA, controller (23 ).
5
Patent
Computer system with cooperative debug circuit for multiple cpu and debug method
Teppei Hirotsu,Yasuhiro Nakatsuka,Masahiko Saito,Kotaro Shimamura,Takahashi Nobutaka,康弘 中塚,光太郎 島村,鉄平 広津,宜孝 高橋,雅彦 齊藤 +9 more
- 28 Nov 2001
TL;DR: In this paper, a break coordination circuit is realized by hardware (a coordinated debug circuit 3) to conduct a strict synchronization of break and step execution of multiple CPU systems, and a brake coordination combination circuit combines brake output signals from CPU, to generate brake input signals to the CPU.
5