What is the rationale of the heuristic?

The rationale of the heuristic lies in the fact that in diagnosis a small number of vectors usually screens the majority of invalid candidates [4] [12].

What is the underlying engine for the automated sequential circuit debugger?

The automated sequential circuit debugger described in the previous sections is implemented in C++ using zChaff [9] as the underlying satisfiability engine.

What is the number of clauses for the counter?

Since the full-adders contribute a constant multiplicative factor of clauses, the authors conclude that the number of clauses for the counter is O(n).

What is the formula for a SAT solver?

Given F ′′, a SAT solver assigns s = 1 and attempts to find a satisfying assignment for the circuit lines and the “free” variables w1,1 and w1,2 so that the circuit emulates the specification for test sequence V 1,2.

What is the binary representation of the integer passed from the adder to the comparator?

Assume that the binary representation of the integer passed from the adder to the comparator is blog n−1 . . . b1b0. A comparator for SAT-based debugging of 2 faults is formed by adding CNF blog n−1 ·blog n−2 · . . . · b2 · b1 · b0 in EN (S).

What is the CNF size for the adder?

The CNF size for the adder is proportional to the number of CNF variables (bits) used to hold the values of the select lines and all intermediate results of the adder tree.

What does the SAT solver do when p is smaller?

On the other hand, smaller values of p enforce less tight constraints and increase the number of potential locations the SAT solver returns.

Open AccessProceedings Article10.1109/MTV.2004.7

Debugging sequential circuits using Boolean satisfiability

Moayad Fahim Ali, +5 more

- 09 Sep 2004

- pp 44-49

TL;DR: An extensive suite of experiments with large sequential circuits confirm the robustness and efficiency of the proposed logic debugging methodology and suggest that Boolean satisfiability provides an effective platform for sequential logic debugging.

Abstract: Logic debugging of today's complex sequential circuits is an important problem. In this paper, a logic debugging methodology for multiple errors in sequential circuits with no state equivalence is developed. The proposed approach reduces the problem of debugging to an instance of Boolean satisfiability. This formulation takes advantage of modern Boolean satisfiability solvers that handle large circuits in a computationally efficient manner. An extensive suite of experiments with large sequential circuits confirm the robustness and efficiency of the proposed approach. The results further suggest that Boolean satisfiability provides an effective platform for sequential logic debugging.

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1. What have the authors contributed in "Debugging sequential circuits using boolean satisfiability" ?

In this paper, a logic debugging methodology for multiple errors in sequential circuits with no state equivalence is developed.. The results further suggest that Boolean Satisfiability provides an effective platform for sequential logic debugging.

2. What are the future works in "Debugging sequential circuits using boolean satisfiability" ?

Theory and experiments confirm its practicality and encourage further research effort towards novel SAT-based debugging techniques.

3. Why is a single set of variables required for a CNF?

only one set of select line variables S = s1, s2, . . . , sn is required because the error locations of a solution must satisfy all vector constraints simultaneously.

4. What is the main reason why automated logic debugging tools are of great benefit?

With 60% of the overall VLSI design cost attributed to verification and debugging, it is evident that automated logic debugging tools are of great benefit.

Figure 7: Run time vs. number of cycles m

Citations

•Journal Article•10.1109/TCAD.2005.852031

Fault diagnosis and logic debugging using Boolean satisfiability

Alex J. Smith, +3 more

- 26 Sep 2005

- IEEE Transactions on Computer-Aided Desi...

TL;DR: This work proposes a novel Boolean satisfiability-based method for multiple-fault diagnosis and multiple-design-error diagnosis in combinational and sequential circuits and suggests that satisfiability captures significant characteristics of the problem of diagnosis.

...read moreread less

292

•Journal Article•10.3233/SAT190055

QBF-Based Formal Verification: Experience and Perspectives

Marco Benedetti, +1 more

- 09 Jul 2008

- Journal on Satisfiability, Boolean Model...

TL;DR: The use and the benefits of restricted quantifiers, QBF certificates, alternative encodings for classical model checking problems, andencodings with free variables are described, which seem to reverse the negative standing of QBF applied to FV.

...read moreread less

108

Journal Article•10.1109/TCAD.2008.923234

Automatic Fault Localization for Property Checking

Görschwin Fey, +3 more

- 01 Jun 2008

- IEEE Transactions on Computer-Aided Desi...

TL;DR: An efficient fully automatic approach to fault localization for safety properties stated in linear temporal logic is presented by solving the satisfiability of a propositional Boolean formula using the proper decision heuristics and simulation-based preprocessing.

...read moreread less

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Journal Issue•10.1002/STVR.V20:2

Fault localization using a model checker

Andreas Griesmayer, +2 more

- 01 Jun 2010

- Software Testing, Verification & Reliabi...

TL;DR: It is shown that model checkers can also be used to perform model-based diagnosis and thus fault localization and leads to significantly more precise diagnoses than the state-of-the-art and typically rules out 90–99p of the code as possible fault locations.

...read moreread less

Journal Article•10.1109/TCAD.2007.907284

ANN- and PSO-Based Synthesis of On-Chip Spiral Inductors for RF ICs

Sushanta K. Mandal, +2 more

- 01 Jan 2008

- IEEE Transactions on Computer-Aided Desi...

TL;DR: The synthesis approach provides multiple sets of layout parameters that help a designer in the tradeoff analysis between conflicting objectives, such as area, Q, and SRF for a target-inductance value.

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...

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References

Proceedings Article•10.1145/378239.379017

Chaff: engineering an efficient SAT solver

Matthew W. Moskewicz, +4 more

- 22 Jun 2001

TL;DR: The development of a new complete solver, Chaff, is described which achieves significant performance gains through careful engineering of all aspects of the search-especially a particularly efficient implementation of Boolean constraint propagation (BCP) and a novel low overhead decision strategy.

...read moreread less

3.5K

•Journal Article•10.1109/12.769433

GRASP: a search algorithm for propositional satisfiability

Joao Marques-Silva, +1 more

- 01 May 1999

- IEEE Transactions on Computers

TL;DR: Experimental results obtained from a large number of benchmarks indicate that application of the proposed conflict analysis techniques to SAT algorithms can be extremely effective for aLarge number of representative classes of SAT instances.

...read moreread less

1.6K

•Book

Testing of Digital Systems

Niraj K. Jha, +1 more

- 15 May 2003

TL;DR: This book is the most comprehensive introduction available to the range of techniques and tools used in digital testing, including fault simulation, CMOS testing, design for testability, and built-in self test.

...read moreread less

357

Book•10.1007/978-3-662-03809-3

Introduction to formal hardware verification

Thomas Kropf

- 01 Jan 1999

TL;DR: This chapter discusses Boolean Functions, Finite State Machine Based Approaches, Propositional Temporal Logics, and Higher Order Logic.

...read moreread less

273

Journal Article•10.1109/43.3141

Logic design verification via test generation

M.S. Abadir, +2 more

- 01 Jan 1988

- IEEE Transactions on Computer-Aided Desi...

TL;DR: A method for logic design verification is introduced in which a gate-level implementation of a circuit is compared with a functional-level specification and it is shown that the class of design errors that can be detected is very large.

...read moreread less

192

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Debugging sequential circuits using Boolean satisfiability

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Most frequently asked questions

1. What have the authors contributed in "Debugging sequential circuits using boolean satisfiability" ?

2. What are the future works in "Debugging sequential circuits using boolean satisfiability" ?

3. Why is a single set of variables required for a CNF?

4. What is the main reason why automated logic debugging tools are of great benefit?

5. What is the rationale of the heuristic?

6. What is the underlying engine for the automated sequential circuit debugger?

7. What is the number of clauses for the counter?

8. What is the formula for a SAT solver?

9. What is the binary representation of the integer passed from the adder to the comparator?

10. What is the CNF size for the adder?

11. What does the SAT solver do when p is smaller?

Figures

Citations

Fault diagnosis and logic debugging using Boolean satisfiability

QBF-Based Formal Verification: Experience and Perspectives

Automatic Fault Localization for Property Checking

Fault localization using a model checker

ANN- and PSO-Based Synthesis of On-Chip Spiral Inductors for RF ICs

References

Chaff: engineering an efficient SAT solver

GRASP: a search algorithm for propositional satisfiability

Testing of Digital Systems

Introduction to formal hardware verification

Logic design verification via test generation

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